#include "netx_drv.h"
#include "netx90_app.h"

Include dependency graph for netx_drv_csp_netx90_app.h:

This graph shows which files directly or indirectly include this file:

Data Structures
union	DRV_SPI_DEVICE_U

Macros
#define	DRIVER_CSP_NETX90_APP_H_

#define	DRV_CORTEX_MODULE_SUPPORTED

#define	DRV_BISS_MODULE_SUPPORTED

#define	DRV_CANCTRL_MODULE_SUPPORTED

#define	DRV_XPIC_MODULE_SUPPORTED

#define	DRV_ETH_XPIC_MODULE_SUPPORTED

#define	DRV_ASIC_CTRL_DEVICE ((DRV_ASIC_CTRL_T*) asic_ctrl_BASE)

#define	DRV_MLED_MODULE_SUPPORTED

#define	DRV_MLED_DEVICE ((DRV_MLED_DEVICE_T*) mled_ctrl_app_BASE)

#define	DRV_MLED_DEVICE_COUNT 1

#define	DRV_MLED_DEVICE_LIST { DRV_MLED_DEVICE }

#define	DRV_MLED_MSK_0 (uint32_t)0x00000001ull

#define	DRV_MLED_MSK_1 (uint32_t)0x00000002ull

#define	DRV_MLED_MSK_2 (uint32_t)0x00000004ull

#define	DRV_MLED_MSK_3 (uint32_t)0x00000008ull

#define	DRV_MLED_MSK_4 (uint32_t)0x00000010ull

#define	DRV_MLED_MSK_5 (uint32_t)0x00000020ull

#define	DRV_MLED_MSK_6 (uint32_t)0x00000040ull

#define	DRV_MLED_MSK_7 (uint32_t)0x00000080ull

#define	DRV_MLED_MSK_8 (uint32_t)0x00000100ull

#define	DRV_MLED_MSK_9 (uint32_t)0x00000200ull

#define	DRV_MLED_MSK_10 (uint32_t)0x00000400ull

#define	DRV_MLED_MSK_11 (uint32_t)0x00000800ull

#define	DRV_MLED_MSK_12 (uint32_t)0x00001000ull

#define	DRV_MLED_MSK_13 (uint32_t)0x00002000ull

#define	DRV_MLED_MSK_14 (uint32_t)0x00004000ull

#define	DRV_MLED_MSK_15 (uint32_t)0x00008000ull

#define	DRV_MLED_LINE_MSK (uint32_t)0x0000FFFFull

#define	DRV_MLED_ID_MIN DRV_MLED_ID_0

#define	DRV_MLED_ID_0 0x000000u

#define	DRV_MLED_ID_1 0x000001u

#define	DRV_MLED_ID_2 0x000002u

#define	DRV_MLED_ID_3 0x000003u

#define	DRV_MLED_ID_4 0x000004u

#define	DRV_MLED_ID_5 0x000005u

#define	DRV_MLED_ID_6 0x000006u

#define	DRV_MLED_ID_7 0x000007u

#define	DRV_MLED_ID_8 0x000008u

#define	DRV_MLED_ID_9 0x000009u

#define	DRV_MLED_ID_10 0x00000au

#define	DRV_MLED_ID_11 0x00000bu

#define	DRV_MLED_ID_12 0x00000cu

#define	DRV_MLED_ID_13 0x00000du

#define	DRV_MLED_ID_14 0x00000eu

#define	DRV_MLED_ID_15 0x00000fu

#define	DRV_MLED_ID_MAX DRV_MLED_ID_15

#define	DRV_DIO_MODULE_SUPPORTED

#define	DRV_MMIO_DEVICE ((DRV_MMIO_DEVICE_T*) mmio_ctrl_BASE)

#define	DRV_HIF_IO_DEVICE ((DRV_HIF_IO_DEVICE_T*) hif_io_ctrl_BASE)

#define	DRV_GPIO_DEVICE ((DRV_GPIO_DEVICE_T*) gpio_app_BASE)

#define	DRV_GPIO_XPIC_DEVICE ((DRV_GPIO_DEVICE_T*) gpio_xpic_app_BASE)

#define	DRV_PIO_DEVICE ((DRV_PIO_DEVICE_T*) pio_app_BASE)

#define	DRV_DIO_PIO_INVERT_SUPPORTED

#define	DRV_DIO_PIO_IRQ_SUPPORTED

#define	DRV_GPIO_IRQ_COUNT 8

#define	DRV_GPIO_IRQ_LIST gpio_app0_IRQn, gpio_app1_IRQn, gpio_app2_IRQn, gpio_app3_IRQn, gpio_app4_IRQn, gpio_app5_IRQn, gpio_app6_IRQn, gpio_app7_IRQn

#define	DRV_GPIO0_IRQ gpio_app0_IRQn

#define	DRV_HIF_IRQ_COUNT 4

#define	DRV_HIFPIO_IRQ hif_pio_arm_IRQn

#define	DRV_PIO_IRQ_COUNT 29

#define	DRV_PIO_IRQ pio0_app_IRQn

#define	DRV_BOD_IRQ bod_IRQn

#define	DRV_BOD_IRQ_COUNT 1

#define	DRV_DIO_IRQ_COUNT DRV_GPIO_IRQ_COUNT + DRV_HIF_IRQ_COUNT + DRV_BOD_IRQ_COUNT + DRV_PIO_IRQ_COUNT

#define	DRV_DIO_LINE_MSK_NONE (uint64_t)0x0000000000000000ull

#define	DRV_DIO_LINE_MSK_GPIO (uint64_t)0x00000000000000FFull

#define	DRV_DIO_LINE_MSK_PIO (uint64_t)0x000000001FFFFFFFull

#define	DRV_DIO_LINE_MSK_MMIO (uint64_t)0x00000000000000FFull

#define	DRV_DIO_LINE_MSK_HIF (uint64_t)0xFE03FFFF0000FFFFull

#define	DRV_DIO_MSK_GPIO_0 (uint64_t)0x0000000000000001ull

#define	DRV_DIO_MSK_GPIO_1 (uint64_t)0x0000000000000002ull

#define	DRV_DIO_MSK_GPIO_2 (uint64_t)0x0000000000000004ull

#define	DRV_DIO_MSK_GPIO_3 (uint64_t)0x0000000000000008ull

#define	DRV_DIO_MSK_GPIO_4 (uint64_t)0x0000000000000010ull

#define	DRV_DIO_MSK_GPIO_5 (uint64_t)0x0000000000000020ull

#define	DRV_DIO_MSK_GPIO_6 (uint64_t)0x0000000000000040ull

#define	DRV_DIO_MSK_GPIO_7 (uint64_t)0x0000000000000080ull

#define	DRV_DIO_MSK_PIO_0 (uint64_t)0x0000000000000001ull

#define	DRV_DIO_MSK_PIO_1 (uint64_t)0x0000000000000002ull

#define	DRV_DIO_MSK_PIO_2 (uint64_t)0x0000000000000004ull

#define	DRV_DIO_MSK_PIO_3 (uint64_t)0x0000000000000008ull

#define	DRV_DIO_MSK_PIO_4 (uint64_t)0x0000000000000010ull

#define	DRV_DIO_MSK_PIO_5 (uint64_t)0x0000000000000020ull

#define	DRV_DIO_MSK_PIO_6 (uint64_t)0x0000000000000040ull

#define	DRV_DIO_MSK_PIO_7 (uint64_t)0x0000000000000080ull

#define	DRV_DIO_MSK_PIO_8 (uint64_t)0x0000000000000100ull

#define	DRV_DIO_MSK_PIO_9 (uint64_t)0x0000000000000200ull

#define	DRV_DIO_MSK_PIO_10 (uint64_t)0x0000000000000400ull

#define	DRV_DIO_MSK_PIO_11 (uint64_t)0x0000000000000800ull

#define	DRV_DIO_MSK_PIO_12 (uint64_t)0x0000000000001000ull

#define	DRV_DIO_MSK_PIO_13 (uint64_t)0x0000000000002000ull

#define	DRV_DIO_MSK_PIO_14 (uint64_t)0x0000000000004000ull

#define	DRV_DIO_MSK_PIO_15 (uint64_t)0x0000000000008000ull

#define	DRV_DIO_MSK_PIO_16 (uint64_t)0x0000000000010000ull

#define	DRV_DIO_MSK_PIO_17 (uint64_t)0x0000000000020000ull

#define	DRV_DIO_MSK_PIO_18 (uint64_t)0x0000000000040000ull

#define	DRV_DIO_MSK_PIO_19 (uint64_t)0x0000000000080000ull

#define	DRV_DIO_MSK_PIO_20 (uint64_t)0x0000000000100000ull

#define	DRV_DIO_MSK_PIO_21 (uint64_t)0x0000000000200000ull

#define	DRV_DIO_MSK_PIO_22 (uint64_t)0x0000000000400000ull

#define	DRV_DIO_MSK_PIO_23 (uint64_t)0x0000000000800000ull

#define	DRV_DIO_MSK_PIO_24 (uint64_t)0x0000000001000000ull

#define	DRV_DIO_MSK_PIO_25 (uint64_t)0x0000000002000000ull

#define	DRV_DIO_MSK_PIO_26 (uint64_t)0x0000000004000000ull

#define	DRV_DIO_MSK_PIO_27 (uint64_t)0x0000000008000000ull

#define	DRV_DIO_MSK_PIO_28 (uint64_t)0x0000000010000000ull

#define	DRV_DIO_MSK_MMIO_0 (uint64_t)0x0000000000000001ull

#define	DRV_DIO_MSK_MMIO_1 (uint64_t)0x0000000000000002ull

#define	DRV_DIO_MSK_MMIO_2 (uint64_t)0x0000000000000004ull

#define	DRV_DIO_MSK_MMIO_3 (uint64_t)0x0000000000000008ull

#define	DRV_DIO_MSK_MMIO_4 (uint64_t)0x0000000000000010ull

#define	DRV_DIO_MSK_MMIO_5 (uint64_t)0x0000000000000020ull

#define	DRV_DIO_MSK_MMIO_6 (uint64_t)0x0000000000000040ull

#define	DRV_DIO_MSK_MMIO_7 (uint64_t)0x0000000000000080ull

#define	DRV_DIO_MSK_HIF_D0 (uint64_t)0x0000000000000001ull

#define	DRV_DIO_MSK_HIF_D1 (uint64_t)0x0000000000000002ull

#define	DRV_DIO_MSK_HIF_D2 (uint64_t)0x0000000000000004ull

#define	DRV_DIO_MSK_HIF_D3 (uint64_t)0x0000000000000008ull

#define	DRV_DIO_MSK_HIF_D4 (uint64_t)0x0000000000000010ull

#define	DRV_DIO_MSK_HIF_D5 (uint64_t)0x0000000000000020ull

#define	DRV_DIO_MSK_HIF_D6 (uint64_t)0x0000000000000040ull

#define	DRV_DIO_MSK_HIF_D7 (uint64_t)0x0000000000000080ull

#define	DRV_DIO_MSK_HIF_D8 (uint64_t)0x0000000000000100ull

#define	DRV_DIO_MSK_HIF_D9 (uint64_t)0x0000000000000200ull

#define	DRV_DIO_MSK_HIF_D10 (uint64_t)0x0000000000000400ull

#define	DRV_DIO_MSK_HIF_D11 (uint64_t)0x0000000000000800ull

#define	DRV_DIO_MSK_HIF_D12 (uint64_t)0x0000000000001000ull

#define	DRV_DIO_MSK_HIF_D13 (uint64_t)0x0000000000002000ull

#define	DRV_DIO_MSK_HIF_D14 (uint64_t)0x0000000000004000ull

#define	DRV_DIO_MSK_HIF_D15 (uint64_t)0x0000000000008000ull

#define	DRV_DIO_MSK_HIF_D_RESERVED (uint64_t)0x00000000FFFF0000ull

#define	DRV_DIO_MSK_HIF_A0 (uint64_t)0x0000000100000000ull

#define	DRV_DIO_MSK_HIF_A1 (uint64_t)0x0000000200000000ull

#define	DRV_DIO_MSK_HIF_A2 (uint64_t)0x0000000400000000ull

#define	DRV_DIO_MSK_HIF_A3 (uint64_t)0x0000000800000000ull

#define	DRV_DIO_MSK_HIF_A4 (uint64_t)0x0000001000000000ull

#define	DRV_DIO_MSK_HIF_A5 (uint64_t)0x0000002000000000ull

#define	DRV_DIO_MSK_HIF_A6 (uint64_t)0x0000004000000000ull

#define	DRV_DIO_MSK_HIF_A7 (uint64_t)0x0000008000000000ull

#define	DRV_DIO_MSK_HIF_A8 (uint64_t)0x0000010000000000ull

#define	DRV_DIO_MSK_HIF_A9 (uint64_t)0x0000020000000000ull

#define	DRV_DIO_MSK_HIF_A10 (uint64_t)0x0000040000000000ull

#define	DRV_DIO_MSK_HIF_A11 (uint64_t)0x0000080000000000ull

#define	DRV_DIO_MSK_HIF_A12 (uint64_t)0x0000100000000000ull

#define	DRV_DIO_MSK_HIF_A13 (uint64_t)0x0000200000000000ull

#define	DRV_DIO_MSK_HIF_A14 (uint64_t)0x0000400000000000ull

#define	DRV_DIO_MSK_HIF_A15 (uint64_t)0x0000800000000000ull

#define	DRV_DIO_MSK_HIF_A16 (uint64_t)0x0001000000000000ull

#define	DRV_DIO_MSK_HIF_A17 (uint64_t)0x0002000000000000ull

#define	DRV_DIO_MSK_HIF_A_RESERVED (uint64_t)0x01fc000000000000ull

#define	DRV_DIO_MSK_HIF_BHEN (uint64_t)0x0200000000000000ull

#define	DRV_DIO_MSK_HIF_RDN (uint64_t)0x0400000000000000ull

#define	DRV_DIO_MSK_HIF_WRN (uint64_t)0x0800000000000000ull

#define	DRV_DIO_MSK_HIF_CSN (uint64_t)0x1000000000000000ull

#define	DRV_DIO_MSK_HIF_RDY (uint64_t)0x2000000000000000ull

#define	DRV_DIO_MSK_HIF_DIRQ (uint64_t)0x4000000000000000ull

#define	DRV_DIO_MSK_HIF_SDCLK (uint64_t)0x8000000000000000ull

#define	DRV_DIO_ID_GPIO_MIN DRV_DIO_ID_GPIO_0

#define	DRV_DIO_ID_GPIO_0 0x100000u

#define	DRV_DIO_ID_GPIO_1 0x100001u

#define	DRV_DIO_ID_GPIO_2 0x100002u

#define	DRV_DIO_ID_GPIO_3 0x100003u

#define	DRV_DIO_ID_GPIO_4 0x100004u

#define	DRV_DIO_ID_GPIO_5 0x100005u

#define	DRV_DIO_ID_GPIO_6 0x100006u

#define	DRV_DIO_ID_GPIO_7 0x100007u

#define	DRV_DIO_ID_GPIO_MAX DRV_DIO_ID_GPIO_7

#define	DRV_DIO_ID_PIO_MIN DRV_DIO_ID_PIO_0

#define	DRV_DIO_ID_PIO_0 0x200000u

#define	DRV_DIO_ID_PIO_1 0x200001u

#define	DRV_DIO_ID_PIO_2 0x200002u

#define	DRV_DIO_ID_PIO_3 0x200003u

#define	DRV_DIO_ID_PIO_4 0x200004u

#define	DRV_DIO_ID_PIO_5 0x200005u

#define	DRV_DIO_ID_PIO_6 0x200006u

#define	DRV_DIO_ID_PIO_7 0x200007u

#define	DRV_DIO_ID_PIO_8 0x200008u

#define	DRV_DIO_ID_PIO_9 0x200009u

#define	DRV_DIO_ID_PIO_10 0x20000au

#define	DRV_DIO_ID_PIO_11 0x20000bu

#define	DRV_DIO_ID_PIO_12 0x20000cu

#define	DRV_DIO_ID_PIO_13 0x20000du

#define	DRV_DIO_ID_PIO_14 0x20000eu

#define	DRV_DIO_ID_PIO_15 0x20000fu

#define	DRV_DIO_ID_PIO_16 0x200010u

#define	DRV_DIO_ID_PIO_17 0x200011u

#define	DRV_DIO_ID_PIO_18 0x200012u

#define	DRV_DIO_ID_PIO_19 0x200013u

#define	DRV_DIO_ID_PIO_20 0x200014u

#define	DRV_DIO_ID_PIO_21 0x200015u

#define	DRV_DIO_ID_PIO_22 0x200016u

#define	DRV_DIO_ID_PIO_23 0x200017u

#define	DRV_DIO_ID_PIO_24 0x200018u

#define	DRV_DIO_ID_PIO_25 0x200019u

#define	DRV_DIO_ID_PIO_26 0x20001au

#define	DRV_DIO_ID_PIO_27 0x20001bu

#define	DRV_DIO_ID_PIO_28 0x20001cu

#define	DRV_DIO_ID_PIO_MAX DRV_DIO_ID_PIO_28

#define	DRV_DIO_ID_MMIO_MIN DRV_DIO_ID_MMIO_0

#define	DRV_DIO_ID_MMIO_0 0x300000u

#define	DRV_DIO_ID_MMIO_1 0x300001u

#define	DRV_DIO_ID_MMIO_2 0x300002u

#define	DRV_DIO_ID_MMIO_3 0x300003u

#define	DRV_DIO_ID_MMIO_4 0x300004u

#define	DRV_DIO_ID_MMIO_5 0x300005u

#define	DRV_DIO_ID_MMIO_6 0x300006u

#define	DRV_DIO_ID_MMIO_7 0x300007u

#define	DRV_DIO_ID_MMIO_MAX DRV_DIO_ID_MMIO_7

#define	DRV_DIO_ID_HIF_MIN DRV_DIO_ID_HIF_D0

#define	DRV_DIO_ID_HIF_D0 0x400000u

#define	DRV_DIO_ID_HIF_D1 0x400001u

#define	DRV_DIO_ID_HIF_D2 0x400002u

#define	DRV_DIO_ID_HIF_D3 0x400003u

#define	DRV_DIO_ID_HIF_D4 0x400004u

#define	DRV_DIO_ID_HIF_D5 0x400005u

#define	DRV_DIO_ID_HIF_D6 0x400006u

#define	DRV_DIO_ID_HIF_D7 0x400007u

#define	DRV_DIO_ID_HIF_D8 0x400008u

#define	DRV_DIO_ID_HIF_D9 0x400009u

#define	DRV_DIO_ID_HIF_D10 0x40000au

#define	DRV_DIO_ID_HIF_D11 0x40000bu

#define	DRV_DIO_ID_HIF_D12 0x40000cu

#define	DRV_DIO_ID_HIF_D13 0x40000du

#define	DRV_DIO_ID_HIF_D14 0x40000eu

#define	DRV_DIO_ID_HIF_D15 0x40000fu

#define	DRV_DIO_ID_HIF_RESERVED0

#define	DRV_DIO_ID_HIF_A0 0x400020u

#define	DRV_DIO_ID_HIF_A1 0x400021u

#define	DRV_DIO_ID_HIF_A2 0x400022u

#define	DRV_DIO_ID_HIF_A3 0x400023u

#define	DRV_DIO_ID_HIF_A4 0x400024u

#define	DRV_DIO_ID_HIF_A5 0x400025u

#define	DRV_DIO_ID_HIF_A6 0x400026u

#define	DRV_DIO_ID_HIF_A7 0x400027u

#define	DRV_DIO_ID_HIF_A8 0x400028u

#define	DRV_DIO_ID_HIF_A9 0x400029u

#define	DRV_DIO_ID_HIF_A10 0x40002au

#define	DRV_DIO_ID_HIF_A11 0x40002bu

#define	DRV_DIO_ID_HIF_A12 0x40002cu

#define	DRV_DIO_ID_HIF_A13 0x40002du

#define	DRV_DIO_ID_HIF_A14 0x40002eu

#define	DRV_DIO_ID_HIF_A15 0x40002fu

#define	DRV_DIO_ID_HIF_A16 0x400030u

#define	DRV_DIO_ID_HIF_A17 0x400031u

#define	DRV_DIO_ID_HIF_RESERVED1

#define	DRV_DIO_ID_HIF_BHEN 0x400039u

#define	DRV_DIO_ID_HIF_RDN 0x40003au

#define	DRV_DIO_ID_HIF_WRN 0x40003bu

#define	DRV_DIO_ID_HIF_CSN 0x40003cu

#define	DRV_DIO_ID_HIF_RDY 0x40003du

#define	DRV_DIO_ID_HIF_DIRQ 0x40003eu

#define	DRV_DIO_ID_HIF_SDCLK 0x40003fu

#define	DRV_DIO_ID_HIF_MAX DRV_DIO_ID_HIF_SDCLK

#define	DRV_DIO_ID_BOD 0x500070u

#define	DRV_TIM_MODULE_SUPPORTED

#define	DRV_TIMER_DEVICE ((DRV_TIMER_DEVICE_T*) timer_app_BASE)

#define	DRV_TIMER_XPIC_DEVICE ((DRV_TIMER_DEVICE_T*) timer_xpic_app_BASE)

#define	DRV_SYSTIME_LT_DEVICE ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_app_BASE)

#define	DRV_SYSTIME_LT_XPIC_DEVICE ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_xpic_app_BASE)

#define	DRV_SYSTIME_DEVICE ((systime_app_Type*) systime_app_BASE)

#define	DRV_GPIO_COUNTER_IRQs gpio_app_timer0_IRQn, gpio_app_timer1_IRQn, gpio_app_timer2_IRQn

#define	DRV_TIMER_IRQs timer_app0_IRQn, timer_app1_IRQn, timer_app2_IRQn

#define	DRV_SYSTIME_COMPARE_IRQ timer_app_systime_s_IRQn

#define	DRV_SYSTICK_IRQ SysTick_IRQn

#define	DRV_TIM_IRQ_COUNT 8u

#define	DRV_TIM_IRQ_LIST { DRV_GPIO_COUNTER_IRQs, DRV_TIMER_IRQs, DRV_SYSTIME_COMPARE_IRQ, DRV_SYSTICK_IRQ }

#define	DRV_DMAC_MODULE_SUPPORTED

#define	DMAC_APP_CH0_DEVICE ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE)

#define	DMAC_APP_CH1_DEVICE ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+1)

#define	DMAC_APP_CH2_DEVICE ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+2)

#define	DMAC_APP_CH3_DEVICE ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+3)

#define	DRV_DMAC_CH_DEVICE_COUNT 4

#define	DRV_DMAC_REG_IRQ dmac_app_IRQn

#define	DRV_DMAC_CH_DEVICE_LIST { DMAC_APP_CH0_DEVICE, DMAC_APP_CH1_DEVICE, DMAC_APP_CH2_DEVICE, DMAC_APP_CH3_DEVICE }

#define	DMAC_APP_REG_DEVICE ((DRV_DMAC_REG_DEVICE_T*) dmac_app_reg_BASE)

#define	DMAC_MUX_APP_DEVICE ((DRV_DMAC_MUX_DEVICE_T*) dmac_mux_app_BASE)

#define	DRV_UART_MODULE_SUPPORTED

#define	UART_DEVICE_SHARED ((DRV_UART_DEVICE_T*) uart_BASE)

#define	DRV_UART_IRQ_HANDLER0 UARTAPP_IRQHandler

#define	UART_DEVICE_APP ((DRV_UART_DEVICE_T*) uart_app_BASE)

#define	DRV_UART_IRQ_HANDLER1 UARTXPIC_IRQHandler

#define	UART_DEVICE_XPIC_APP ((DRV_UART_DEVICE_T*) uart_xpic_app_BASE)

#define	DRV_UART_IRQ_HANDLER2 UART_IRQHandler

#define	DRV_UART_DEVICE_COUNT 3

#define	DRV_UART_DEVICE_LIST { UART_DEVICE_APP, UART_DEVICE_XPIC_APP, UART_DEVICE_SHARED }

#define	DRV_UART_DEVICE_IRQ_LIST { uart_app_IRQn, uart_xpic_app_IRQn, uart_IRQn }

#define	DRV_UART_DEVICE_DMA_LIST { DRV_DMAC_PERIPHERAL_UART_APP_RX, DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_UART_SHARED_RX }

#define	DRV_SPI_MODULE_SUPPORTED

#define	DRV_SPI_IRQ_HANDLER0 SPI0_IRQHandler

#define	DRV_SPI_IRQ_HANDLER1 SPI1_IRQHandler

#define	DRV_SPI_IRQ_HANDLER2 SPI2_IRQHandler

#define	DRV_SPI_IRQ_HANDLER3 SPIXPIC_IRQHandler

#define	DRV_SPI_IRQ_HANDLER4 SQI_IRQHandler

#define	DRV_SPI_IRQ_HANDLER5 SQI0_IRQHandler

#define	DRV_SPI_IRQ_HANDLER6 SQI1_IRQHandler

#define	SPI_DEVICE_APP0 ((DRV_SPI_DEVICE_T*) spi0_app_BASE)

#define	SPI_DEVICE_APP1 ((DRV_SPI_DEVICE_T*) spi1_app_BASE)

#define	SPI_DEVICE_APP2 ((DRV_SPI_DEVICE_T*) spi2_app_BASE)

#define	SPI_DEVICE_APP3 ((DRV_SPI_DEVICE_T*) spi_xpic_app_BASE)

#define	SQI_DEVICE_SHARED ((DRV_SQI_DEVICE_T*) sqi_BASE)

#define	SQI_DEVICE_APP0 ((DRV_SQI_DEVICE_T*) sqi0_app_BASE)

#define	SQI_DEVICE_APP1 ((DRV_SQI_DEVICE_T*) sqi1_app_BASE)

#define	DRV_SPI_DEVICE_COUNT 7

#define	DRV_SPI_DEVICE_LIST { {(uintptr_t) SPI_DEVICE_APP0}, {(uintptr_t) SPI_DEVICE_APP1}, {(uintptr_t) SPI_DEVICE_APP2}, {(uintptr_t) SPI_DEVICE_APP3}, {(uintptr_t) SQI_DEVICE_SHARED}, {(uintptr_t) SQI_DEVICE_APP0}, {(uintptr_t) SQI_DEVICE_APP1}}

#define	DRV_SPI_DEVICE_IRQ_LIST { spi0_app_IRQn, spi1_app_IRQn, spi2_app_IRQn, spi_xpic_app_IRQn, sqi_IRQn, sqi0_app_IRQn, sqi1_app_IRQn }

#define	DRV_SPI_DEVICE_DMA_LIST { DRV_DMAC_PERIPHERAL_SPI0_APP_RX, DRV_DMAC_PERIPHERAL_SPI1_APP_RX, DRV_DMAC_PERIPHERAL_SPI2_APP_RX, DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_SQI_RX, DRV_DMAC_PERIPHERAL_SQI0_APP_RX, DRV_DMAC_PERIPHERAL_SQI1_APP_RX }

#define	DRV_I2C_MODULE_SUPPORTED

#define	I2C_DEVICE_APP0 ((DRV_I2C_DEVICE_T*) i2c_app_BASE)

#define	DRV_I2C_IRQ_HANDLER0 I2C_IRQHandler

#define	I2C_DEVICE_APP1 ((DRV_I2C_DEVICE_T*) i2c_xpic_app_BASE)

#define	DRV_I2C_IRQ_HANDLER1 I2CXPIC_IRQHandler

#define	DRV_I2C_DEVICE_COUNT 2

#define	DRV_I2C_DEVICE_LIST { I2C_DEVICE_APP0, I2C_DEVICE_APP1 }

#define	DRV_I2C_DEVICE_IRQ_LIST { i2c_app_IRQn, i2c_xpic_app_IRQn }

#define	ADC_APP_DEVICE ((DRV_ADC_DEVICE_T*) madc_BASE)

#define	ADC_SEQ0_APP_DEVICE ((DRV_ADC_SEQ_DEVICE_T*) madc_seq0_BASE)

#define	ADC_SEQ1_APP_DEVICE ((DRV_ADC_SEQ_DEVICE_T*) madc_seq1_BASE)

#define	ADC_SEQ2_APP_DEVICE ((DRV_ADC_SEQ_DEVICE_T*) madc_seq2_BASE)

#define	ADC_SEQ3_APP_DEVICE ((DRV_ADC_SEQ_DEVICE_T*) madc_seq3_BASE)

#define	DRV_ADC_DEVICE_COUNT 1

#define	DRV_ADC_DEVICE_LIST { ADC_APP_DEVICE }

#define	DRV_ADC_SEQ_DEVICE_COUNT 4

#define	DRV_ADC_SEQ_DEVICE_LIST { ADC_SEQ0_APP_DEVICE, ADC_SEQ1_APP_DEVICE, ADC_SEQ2_APP_DEVICE, ADC_SEQ3_APP_DEVICE }

#define	DRV_ADC_SEQ_DEVICE_IRQ_LIST { madc_seq0_IRQn, madc_seq1_IRQn, madc_seq2_IRQn, madc_seq3_IRQn }

#define	DRV_ADC_COUNT 4

#define	DRV_ADC_INPUTS_MAX 8

#define	DRV_ADC_MEASUREMENTS_MAX 8

#define	DRV_ADC_INPUT_COUNT01 4

#define	DRV_ADC_INPUT_COUNT23 8

#define	DRV_ADC_MODULE_SUPPORTED

Typedefs
typedef asic_ctrl_Type	DRV_ASIC_CTRL_T

typedef mled_ctrl_app_Type	DRV_MLED_DEVICE_T

typedef mmio_ctrl_Type	DRV_MMIO_DEVICE_T

typedef hif_io_ctrl_Type	DRV_HIF_IO_DEVICE_T

typedef gpio_app_Type	DRV_GPIO_DEVICE_T

typedef pio_app_Type	DRV_PIO_DEVICE_T

typedef timer_app_Type	DRV_TIMER_DEVICE_T

typedef systime_lt_app_Type	DRV_SYSTIME_LT_DEVICE_T

typedef systime_app_Type	DRV_SYSTIME_DEVICE_T

typedef dmac_app_ch_Type	DRV_DMAC_CH_DEVICE_T

typedef dmac_app_reg_Type	DRV_DMAC_REG_DEVICE_T

typedef dmac_mux_app_Type	DRV_DMAC_MUX_DEVICE_T

typedef uart_app_Type	DRV_UART_DEVICE_T

typedef spi0_app_Type	DRV_SPI_DEVICE_T

typedef sqi_Type	DRV_SQI_DEVICE_T

typedef i2c_app_Type	DRV_I2C_DEVICE_T

typedef madc_Type	DRV_ADC_DEVICE_T

typedef madc_seq0_Type	DRV_ADC_SEQ_DEVICE_T

Enumerations
enum	DRV_TIM_DEVICE_ID_E { DRV_TIM_DEVICE_ID_GPIOCNTR0 = 0x10ul, DRV_TIM_DEVICE_ID_GPIOCNTR1 = 0x11ul, DRV_TIM_DEVICE_ID_GPIOCNTR2 = 0x12ul, DRV_TIM_DEVICE_ID_GPIOCNTR_MIN = DRV_TIM_DEVICE_ID_GPIOCNTR0, DRV_TIM_DEVICE_ID_GPIOCNTR_MAX = DRV_TIM_DEVICE_ID_GPIOCNTR2, DRV_TIM_DEVICE_ID_TIMER0 = 0x13ul, DRV_TIM_DEVICE_ID_TIMER1 = 0x14ul, DRV_TIM_DEVICE_ID_TIMER2 = 0x15ul, DRV_TIM_DEVICE_ID_TIMER_MIN = DRV_TIM_DEVICE_ID_TIMER0, DRV_TIM_DEVICE_ID_TIMER_MAX = DRV_TIM_DEVICE_ID_TIMER2, DRV_TIM_DEVICE_ID_SYSTIMECOMPARE = 0x16ul, DRV_TIM_DEVICE_ID_SYSTICK = 0x17ul, DRV_TIM_DEVICE_ID_SYSTIME_COM = 0x18ul, DRV_TIM_DEVICE_ID_SYSTIME_COM_UC = 0x19ul, DRV_TIM_DEVICE_ID_SYSTIME_APP = 0x1aul, DRV_TIM_DEVICE_ID_SYSTIME_MIN = DRV_TIM_DEVICE_ID_SYSTIME_COM, DRV_TIM_DEVICE_ID_SYSTIME_MAX = DRV_TIM_DEVICE_ID_SYSTIME_APP, DRV_TIM_DEVICE_ID_MIN = DRV_TIM_DEVICE_ID_GPIOCNTR0, DRV_TIM_DEVICE_ID_MAX = DRV_TIM_DEVICE_ID_SYSTIME_APP }
	Enumeration of the available timer IDs. More...

enum	DRV_DMAC_DEVICE_ID_E { DRV_DMAC_DEVICE_ID_0 = 0x8u, DRV_DMAC_DEVICE_ID_1 = 0x9u, DRV_DMAC_DEVICE_ID_2 = 0xau, DRV_DMAC_DEVICE_ID_3 = 0xbu, DRV_DMAC_DEVICE_ID_MIN = DRV_DMAC_DEVICE_ID_0, DRV_DMAC_DEVICE_ID_MAX = DRV_DMAC_DEVICE_ID_3 }

enum	DRV_DMAC_PERIPHERAL_E { DRV_DMAC_PERIPHERAL_UART_SHARED_RX = 0u, DRV_DMAC_PERIPHERAL_UART_SHARED_TX = 1u, DRV_DMAC_PERIPHERAL_UART_APP_RX = 2u, DRV_DMAC_PERIPHERAL_UART_APP_TX = 3u, DRV_DMAC_PERIPHERAL_I2C_APP_MASTER = 4u, DRV_DMAC_PERIPHERAL_I2C_APP_SLAVE = 5u, DRV_DMAC_PERIPHERAL_SPI0_APP_RX = 6u, DRV_DMAC_PERIPHERAL_SPI0_APP_TX = 7u, DRV_DMAC_PERIPHERAL_SPI1_APP_RX = 8u, DRV_DMAC_PERIPHERAL_SPI1_APP_TX = 9u, DRV_DMAC_PERIPHERAL_SPI2_APP_RX = 10u, DRV_DMAC_PERIPHERAL_SPI2_APP_TX = 11u, DRV_DMAC_PERIPHERAL_SQI0_APP_RX = 12u, DRV_DMAC_PERIPHERAL_SQI0_APP_TX = 13u, DRV_DMAC_PERIPHERAL_SQI1_APP_RX = 14u, DRV_DMAC_PERIPHERAL_SQI1_APP_TX = 15u, DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX = 16u, DRV_DMAC_PERIPHERAL_UART_XPIC_APP_TX = 17u, DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_MASTER = 18u, DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_SLAVE = 19u, DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX = 20u, DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_TX = 21u, DRV_DMAC_PERIPHERAL_SQI_RX = 22u, DRV_DMAC_PERIPHERAL_SQI_TX = 23u, DRV_DMAC_PERIPHERAL_ETH_RX = 24u, DRV_DMAC_PERIPHERAL_ETH_TX = 25u, DRV_DMAC_PERIPHERAL_HASH = 26u, DRV_DMAC_PERIPHERAL_AES_IN = 27u, DRV_DMAC_PERIPHERAL_AES_OUT = 28u, DRV_DMAC_PERIPHERAL_NC = 29u, DRV_DMAC_PERIPHERAL_30_RESERVED = 30u, DRV_DMAC_PERIPHERAL_31_RESERVED = 31u, DRV_DMAC_PERIPHERAL_MEMORY = 32u }

enum	DRV_UART_DEVICE_ID_E { DRV_UART_DEVICE_ID_UART0 = 0x07ul, DRV_UART_DEVICE_ID_UART1 = 0x08ul, DRV_UART_DEVICE_ID_UART2 = 0x09ul, DRV_UART_DEVICE_ID_MIN = DRV_UART_DEVICE_ID_UART0, DRV_UART_DEVICE_ID_MAX = DRV_UART_DEVICE_ID_UART2 }

enum	DRV_SPI_DEVICE_ID_E { DRV_SPI_DEVICE_ID_DEFAULT = 0x00ul, DRV_SPI_DEVICE_ID_SPI0 = 0x10ul, DRV_SPI_DEVICE_ID_SPI1 = 0x11ul, DRV_SPI_DEVICE_ID_SPI2 = 0x12ul, DRV_SPI_DEVICE_ID_SPI3 = 0x13ul, DRV_SPI_DEVICE_ID_SQI0 = 0x14ul, DRV_SPI_DEVICE_ID_SQI1 = 0x15ul, DRV_SPI_DEVICE_ID_SQI2 = 0x16ul, DRV_SPI_DEVICE_ID_MIN = DRV_SPI_DEVICE_ID_SPI0, DRV_SPI_DEVICE_ID_MAX = DRV_SPI_DEVICE_ID_SQI2, DRV_SPI_DEVICE_ID_SQI_BORDER = DRV_SPI_DEVICE_ID_SQI0, DRV_SPI_DEVICE_ID_QSPI_BORDER = DRV_SPI_DEVICE_ID_MAX+1 }
	The SPI device IDs. More...

enum	DRV_I2C_DEVICE_ID_E { DRV_I2C_DEVICE_ID_I2C0 = 0x1ul, DRV_I2C_DEVICE_ID_I2C1 = 0x02ul, DRV_I2C_DEVICE_ID_MIN = DRV_I2C_DEVICE_ID_I2C0, DRV_I2C_DEVICE_ID_MAX = DRV_I2C_DEVICE_ID_I2C1 }

enum	DRV_ADC_SEQ_DEVICE_ID_E { DRV_ADC_SEQ_DEVICE_ID_ADC0 = 0x10u, DRV_ADC_SEQ_DEVICE_ID_ADC1 = 0x11u, DRV_ADC_SEQ_DEVICE_ID_ADC2 = 0x12u, DRV_ADC_SEQ_DEVICE_ID_ADC3 = 0x13u, DRV_ADC_SEQ_DEVICE_ID_MIN = DRV_ADC_SEQ_DEVICE_ID_ADC0, DRV_ADC_SEQ_DEVICE_ID_MAX = DRV_ADC_SEQ_DEVICE_ID_ADC3 }

Macro Definition Documentation

#define DRIVER_CSP_NETX90_APP_H_

Definition at line 22 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER0 SPI0_IRQHandler

Definition at line 478 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER1 SPI1_IRQHandler

Definition at line 480 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER2 SPI2_IRQHandler

Definition at line 482 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER3 SPIXPIC_IRQHandler

Definition at line 484 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER4 SQI_IRQHandler

Definition at line 486 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER5 SQI0_IRQHandler

Definition at line 488 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_IRQ_HANDLER6 SQI1_IRQHandler

Definition at line 490 of file netx_drv_csp_netx90_app.h.

Data Structures

Macros

Typedefs

Enumerations

Macro Definition Documentation