 |
Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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|
Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
i2c_app (i2c_app) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IOM uint32_t i2c_mcr | |
| struct { | |
| __IOM uint32_t en_i2c: 1 | |
| __IOM uint32_t mode: 3 | |
| __IOM uint32_t sadr: 7 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t pio_mode: 1 | |
| __IOM uint32_t rst_i2c: 1 | |
| __IOM uint32_t en_timeout: 1 | |
| __IOM uint32_t bf_align1: 13 | |
| } i2c_mcr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_scr | |
| struct { | |
| __IOM uint32_t sid: 10 | |
| __IOM uint32_t sid10: 1 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t ac_srx: 1 | |
| __IOM uint32_t ac_start: 1 | |
| __IOM uint32_t ac_gcall: 1 | |
| __IOM uint32_t bf_align1: 1 | |
| __IOM uint32_t autoreset_ac_start: 1 | |
| __IOM uint32_t bf_align2: 11 | |
| } i2c_scr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_cmd | |
| struct { | |
| __IOM uint32_t nwr: 1 | |
| __IOM uint32_t cmd: 3 | |
| __IOM uint32_t bf_align0: 4 | |
| __IOM uint32_t tsize: 10 | |
| __IOM uint32_t bf_align1: 2 | |
| __IOM uint32_t acpollmax: 8 | |
| __IOM uint32_t bf_align2: 4 | |
| } i2c_cmd_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_mdr | |
| struct { | |
| __IOM uint32_t mdata: 8 | |
| __IOM uint32_t bf_align0: 24 | |
| } i2c_mdr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_sdr | |
| struct { | |
| __IOM uint32_t sdata: 8 | |
| __IOM uint32_t bf_align0: 24 | |
| } i2c_sdr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_mfifo_cr | |
| struct { | |
| __IOM uint32_t mfifo_wm: 4 | |
| __IOM uint32_t bf_align0: 4 | |
| __IOM uint32_t mfifo_clr: 1 | |
| __IOM uint32_t bf_align1: 23 | |
| } i2c_mfifo_cr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_sfifo_cr | |
| struct { | |
| __IOM uint32_t sfifo_wm: 4 | |
| __IOM uint32_t bf_align0: 4 | |
| __IOM uint32_t sfifo_clr: 1 | |
| __IOM uint32_t bf_align1: 23 | |
| } i2c_sfifo_cr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_sr | |
| struct { | |
| __IOM uint32_t mfifo_level: 5 | |
| __IOM uint32_t bf_align0: 1 | |
| __IOM uint32_t mfifo_empty: 1 | |
| __IOM uint32_t mfifo_full: 1 | |
| __IOM uint32_t mfifo_err_ovfl: 1 | |
| __IOM uint32_t mfifo_err_undr: 1 | |
| __IOM uint32_t sfifo_level: 5 | |
| __IOM uint32_t bf_align1: 1 | |
| __IOM uint32_t sfifo_empty: 1 | |
| __IOM uint32_t sfifo_full: 1 | |
| __IOM uint32_t sfifo_err_ovfl: 1 | |
| __IOM uint32_t sfifo_err_undr: 1 | |
| __IOM uint32_t bus_master: 1 | |
| __IOM uint32_t nwr: 1 | |
| __IOM uint32_t started: 1 | |
| __IOM uint32_t slave_access: 1 | |
| __IOM uint32_t last_ac: 1 | |
| __IOM uint32_t nwr_aced: 1 | |
| __IOM uint32_t gcall_aced: 1 | |
| __IOM uint32_t sid10_aced: 1 | |
| __IOM uint32_t timeout: 1 | |
| __IOM uint32_t bf_align2: 1 | |
| __IOM uint32_t scl_state: 1 | |
| __IOM uint32_t sda_state: 1 | |
| } i2c_sr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_irqmsk | |
| struct { | |
| __IOM uint32_t cmd_ok: 1 | |
| __IOM uint32_t cmd_err: 1 | |
| __IOM uint32_t fifo_err: 1 | |
| __IOM uint32_t bus_busy: 1 | |
| __IOM uint32_t mfifo_req: 1 | |
| __IOM uint32_t sfifo_req: 1 | |
| __IOM uint32_t sreq: 1 | |
| __IOM uint32_t bf_align0: 25 | |
| } i2c_irqmsk_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_irqsr | |
| struct { | |
| __IOM uint32_t cmd_ok: 1 | |
| __IOM uint32_t cmd_err: 1 | |
| __IOM uint32_t fifo_err: 1 | |
| __IOM uint32_t bus_busy: 1 | |
| __IOM uint32_t mfifo_req: 1 | |
| __IOM uint32_t sfifo_req: 1 | |
| __IOM uint32_t sreq: 1 | |
| __IOM uint32_t bf_align0: 25 | |
| } i2c_irqsr_b | |
| }; | |
| union { | |
| __IM uint32_t i2c_irqmsked | |
| struct { | |
| __IM uint32_t cmd_ok: 1 | |
| __IM uint32_t cmd_err: 1 | |
| __IM uint32_t fifo_err: 1 | |
| __IM uint32_t bus_busy: 1 | |
| __IM uint32_t mfifo_req: 1 | |
| __IM uint32_t sfifo_req: 1 | |
| __IM uint32_t sreq: 1 | |
| __IM uint32_t bf_align0: 25 | |
| } i2c_irqmsked_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_dmacr | |
| struct { | |
| __IOM uint32_t mdmas_en: 1 | |
| __IOM uint32_t mdmab_en: 1 | |
| __IOM uint32_t sdmas_en: 1 | |
| __IOM uint32_t sdmab_en: 1 | |
| __IOM uint32_t bf_align0: 28 | |
| } i2c_dmacr_b | |
| }; | |
| union { | |
| __IOM uint32_t i2c_pio | |
| struct { | |
| __IOM uint32_t scl_out: 1 | |
| __IOM uint32_t scl_oe: 1 | |
| __IOM uint32_t scl_in_ro: 1 | |
| __IOM uint32_t bf_align0: 1 | |
| __IOM uint32_t sda_out: 1 | |
| __IOM uint32_t sda_oe: 1 | |
| __IOM uint32_t sda_in_ro: 1 | |
| __IOM uint32_t bf_align1: 25 | |
| } i2c_pio_b | |
| }; | |
i2c_app (i2c_app)
Definition at line 20564 of file netx90_app.h.
| union { ... } |
< (@ 0xFF801080) i2c_app Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IOM uint32_t i2c_app_Type::ac_gcall |
[18..18] General call acknowledge: 0: Do not generate an acknowledge after a general call 1: Generate an acknowledge after a general call
Definition at line 20644 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::ac_srx |
[16..16] Enable slave-receive-data acknowledge: 0: Do not acknowledge receive bytes 1: Acknowledge receive bytes If the slave FIFO is full, receive data will not be acknowledged.
Definition at line 20632 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::ac_start |
[17..17] Enable start sequence acknowledge: If the received address matches the sid-bits, the start-byte (2 bytes if sid10 is set) will be acknowledged. If the master requests a read transfer, a slave FIFO read access will be carried out immediately after the acknowledge, i.e. valid data must be present in the slave FIFO before enabling the acknowledge. If autoreset_ac_start is enabled, the controller will automatically reset this bit. If it is not enabled, the software should reset this bit after the start sequenc
Definition at line 20635 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::acpollmax |
[27..20] Number of tries (acpollmax+1, i.e. 1 to 256) for start sequence acknowledge polling: For 7-bit addressing, acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up to acpollmax+1 times until a slave generates an acknowledge. If no acknowledge is received within acpollmax+1 tries, IRQ cmd_err will be generated. For 10-bit-addressing, the 2-byte start sequence is performed. The second address byte (lower address bits) must be on top of the master FIFO (i2c_
Definition at line 20683 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::autoreset_ac_start |
[20..20] Auto reset ac_start (ac_start must be set again after any (r)START): 0: ac_start will not be reset automatically (netX 50-compatible, but not recommended) 1: Reset ac_start after this slave acknowledged a start sequence (recommended)
Definition at line 20648 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::bf_align0 |
[15..11] bitField alignment value for aeabi compatibility
[7..4] bitField alignment value for aeabi compatibility
[31..8] bitField alignment value for aeabi compatibility
[5..5] bitField alignment value for aeabi compatibility
[31..7] bitField alignment value for aeabi compatibility
[31..4] bitField alignment value for aeabi compatibility
[3..3] bitField alignment value for aeabi compatibility
Definition at line 20597 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::bf_align0 |
[31..7] bitField alignment value for aeabi compatibility
Definition at line 20969 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::bf_align1 |
[31..19] bitField alignment value for aeabi compatibility
[19..19] bitField alignment value for aeabi compatibility
[19..18] bitField alignment value for aeabi compatibility
[31..9] bitField alignment value for aeabi compatibility
[15..15] bitField alignment value for aeabi compatibility
[31..7] bitField alignment value for aeabi compatibility
Definition at line 20616 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::bf_align2 |
[31..21] bitField alignment value for aeabi compatibility
[31..28] bitField alignment value for aeabi compatibility
[29..29] bitField alignment value for aeabi compatibility
Definition at line 20652 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::bus_busy |
[3..3] External I2C-bus is busy interrupt mask
[3..3] Unmasked external I2C-bus is busy interrupt state: Purpose: Detect I2C-bus arbitration loss 1: Master did not gain the requested bus access because another master accessed the bus 0: Bus is idle or no transfer is requested by this master
Definition at line 20909 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::bus_busy |
[3..3] Masked external I2C-bus is busy interrupt state
Definition at line 20965 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::bus_master |
[20..20] Bus arbitration state. 0: Master lost I2C bus arbitration, bus is busy by another master. 1: Master gains I2C bus arbitration or bus is idle. This read-only status bit is set when the monitored bus state does not match the bus state expected by the I2C module. The bit is reset, when a STOP is detected. This detection will also take place while the module is disabled. This is important if there are multiple I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the I2C
Definition at line 20811 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::cmd |
[3..1] I2C sequence command: All commands will generate IRQ cmd_ok or IRQ cmd_err. A successful command termination will always generate IRQ cmd_ok. In case of an unsuccessful command termination, IRQ cmd_err will be set. { | | 000 START Generate (r)START-condition 001 S_AC Acknowledge-polling: generate up to acpollmax+1 START-sequences (until acknowledged by slave) 010 S_AC_T Run S_AC, then transfer tsize+1 bytes from/to master FIFO. Not to be continued 011 S_AC_TC Run S_AC, then tra
Definition at line 20664 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::cmd_err |
[1..1] Command error interrupt mask
[1..1] Unmasked command error interrupt state: Purpose: Check last command termination 1: Last command finished erroneously 0: Command not finished, no command or command finished successfully
Definition at line 20907 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::cmd_err |
[1..1] Masked command error interrupt state
Definition at line 20963 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::cmd_ok |
[0..0] Command OK interrupt mask
[0..0] Unmasked command OK interrupt state: Purpose: Check last command termination 1: Last command finished successfully 0: Command not finished, no command or command finished erroneously
Definition at line 20906 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::cmd_ok |
[0..0] Masked command OK interrupt state
Definition at line 20962 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::en_i2c |
[0..0] Global I2C controller enable 1: Enable I2C controller 0: Disable I2C controller Disabling the I2C module during a transfer will immediately disconnect the I2C module from the bus without generating a STOP. The internal I2C state machine will be set back to initial/idle state. The I2C bus-state-detection for the bits i2c_sr.bus_master and i2c_sr.started are performed even if the module is disabled. For details, see these bits.
Definition at line 20570 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::en_timeout |
[18..18] Enable I2C command timeout detection. Enabling the timeout detection is recommended to prevent the module from stalling if another device holds the I2C signals permanently low. For details, see the description of bit i2s_sr.timeout.
Definition at line 20612 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::fifo_err |
[2..2] FIFO error interrupt mask
[2..2] Unmasked FIFO error interrupt state: Purpose: Detect FIFO errors/transfer failures 1: FIFO error occurred, check register i2c_sr 0: FIFOs ok
Definition at line 20908 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::fifo_err |
[2..2] Masked FIFO error interrupt state
Definition at line 20964 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::gcall_aced |
[26..26] General call acknowledge state. 0: No general call start-byte, or general call start-byte was not acknowledged. 1: The slave side of the i2c module received and acknowledged a general call. Bit i2c_scr.ac_gcall controls the acknowledging of a general call. This read-only status bit will be cleared automatically if the last start-byte is not a general call or if it is a general call but bit i2c_scr.ac_gcall is not set. This bit is forced to '0' when the bit i2c_mcr.rst_i2c performs a reset of the bus-state-
Definition at line 20860 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::i2c_cmd |
(@ 0x00000008) I2C master command register:
Definition at line 20657 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_cmd_b |
| __IOM uint32_t i2c_app_Type::i2c_dmacr |
(@ 0x0000002C) I2C DMA control register: Required settings for the DMA controller: - DMA transfer size to/from I2C module: Byte - DMA burst length to/from I2C module: 4 DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes (receive case) or if more than 4 bytes are writable to the corresponding FIFO (transmit case). DMA single transfer requests will be generated if the corresponding FIFO contains more than 1 byte (receive case) or if more than 1 byte is writable to the c
Definition at line 20974 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_dmacr_b |
| __IOM uint32_t i2c_app_Type::i2c_irqmsk |
(@ 0x00000020) I2C interrupt mask set or clear register: These bits have AND-mask character. The corresponding IRQ will generate the module IRQ only if the mask bit is set. Changing a mask bit from '0' to '1' will clear the corresponding raw IRQ state. For a detailed IRQ description, see i2c_irqraw.
Definition at line 20897 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_irqmsk_b |
| __IM uint32_t i2c_app_Type::i2c_irqmsked |
(@ 0x00000028) I2C masked interrupt state register: If one of these bits is set, the I2C IRQ will be set to the interrupt controller. For a detailed IRQ description, see i2c_irqraw.
Definition at line 20956 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_irqmsked_b |
| __IOM uint32_t i2c_app_Type::i2c_irqsr |
(@ 0x00000024) I2C interrupt state register (raw interrupt before masking): Writing '1' will clear the corresponding IRQ.
Definition at line 20918 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_irqsr_b |
| __IOM uint32_t i2c_app_Type::i2c_mcr |
(@ 0x00000000) I2C master control register:
Definition at line 20567 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_mcr_b |
| __IOM uint32_t i2c_app_Type::i2c_mdr |
(@ 0x0000000C) I2C master data register (master FIFO): There is only one FIFO for both receive and transmit master data with a depth of 16 bytes. For master write access, data sent by the master is delivered from the FIFO. For master read access, data received by the master is stored in the FIFO. In case of imminent data transfer failure (read transfer and FIFO is full or write transfer and FIFO is empty), the transfer will be interrupted. To continue the transfer, the FIFO must be handled first (filled fo
Definition at line 20697 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_mdr_b |
| __IOM uint32_t i2c_app_Type::i2c_mfifo_cr |
(@ 0x00000014) I2C master FIFO control register:
Definition at line 20743 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_mfifo_cr_b |
| __IOM uint32_t i2c_app_Type::i2c_pio |
(@ 0x00000030) PIO mode register: This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr. In PIO mode, the I2C controller state machine is disabled, thus, no FIFO action takes place, no IRQs will be set, and no DMA-controlling is possible. Note: To avoid external driving conflicts, the I2C signals SCL and SDA are never driven active-high according to the I2C bus specification. The high level of these signals is realized by a pull-up (of the pad or external
Definition at line 21009 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_pio_b |
| __IOM uint32_t i2c_app_Type::i2c_scr |
(@ 0x00000004) I2C slave control register:
Definition at line 20621 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_scr_b |
| __IOM uint32_t i2c_app_Type::i2c_sdr |
(@ 0x00000010) I2C slave data register (slave FIFO): There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes. For master read access, data sent by the slave is delivered from the FIFO. For master write access, data received by the slave is stored in the FIFO. A transfer is initiated after the detection of I2C-start-sequence to the device address (i2c_scr.sid, sreq IRQ) which is acknowledged by this device (i2c_scr.ac_start). For read transfers, sent data is read from the FI
Definition at line 20721 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_sdr_b |
| __IOM uint32_t i2c_app_Type::i2c_sfifo_cr |
(@ 0x00000018) I2C slave FIFO control register:
Definition at line 20761 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_sfifo_cr_b |
| __IOM uint32_t i2c_app_Type::i2c_sr |
(@ 0x0000001C) I2C status register:
Definition at line 20778 of file netx90_app.h.
| struct { ... } i2c_app_Type::i2c_sr_b |
| __IOM uint32_t i2c_app_Type::last_ac |
[24..24] Last acknowledge detected on bus. 0: SDA was high at the last acknowledge, i.e. no acknowledge. 1: SDA was low at the last acknowledge, i.e. acknowledge. This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Definition at line 20847 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mdata |
[7..0] I2C master transmit or receive data: Write data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge. Write data that has not been acknowledged will not be removed from the FIFO.
Definition at line 20711 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mdmab_en |
[1..1] Enable DMA burst requests for I2C master data. The I2C module is the flow controller (i.e. peripheral-controlled flow control). Both, single and burst requests must be enabled. This bit is writable, but can also be changed by hardware.
Definition at line 20993 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mdmas_en |
[0..0] Enable DMA single requests for I2C master data. The I2C module is the flow controller (i.e. peripheral-controlled flow control). Both, single and burst requests must be enabled. This bit is writable, but can also be changed by hardware.
Definition at line 20988 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_clr |
[8..8] Clear master data FIFO, write only bit. This bit is writable, but can also be changed by hardware.
Definition at line 20754 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_empty |
[6..6] Master FIFO is empty (1 if empty) This is a read-only status bit.
Definition at line 20784 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_err_ovfl |
[8..8] Master FIFO overflow error occurred. Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
Definition at line 20788 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_err_undr |
[9..9] Master FIFO underrun error occurred. Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
Definition at line 20792 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_full |
[7..7] Master FIFO is full (1 if full) This is a read-only status bit.
Definition at line 20786 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_level |
[4..0] Master FIFO level (0..16) This is a read-only status bit field.
Definition at line 20781 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_req |
[4..4] Master FIFO action request interrupt mask
[4..4] Unmasked master FIFO action request interrupt state: Purpose: Master FIFO should be updated 1: Master FIFO request: i2c_sr.mfifo_level is above or below i2c_mfifo_cr.mfifo_wm (see description i2c_mfifo_cr) 0: Master FIFO state not critical
Definition at line 20910 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::mfifo_req |
[4..4] Masked master FIFO action request interrupt state
Definition at line 20966 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mfifo_wm |
[3..0] Master FIFO watermark for the generation of IRQ mfifo_req: If the master is the transmitter (enabled and i2c_cmd.nwr is 0), IRQ mfifo_req is generated if mfifo_level<mfifo_wm. If the master is the receiver (enabled and i2c_cmd.nwr is 1), IRQ mfifo_req is generated if mfifo_level>mfifo_wm. Note: Set the watermark to 0 at transfer end to avoid further IRQ generation.
Definition at line 20746 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::mode |
[3..1] I2C-speed-mode: If this device is used as a slave only, the mode should be set to the data rate generated by the fastest master on the I2C-bus for appropriate input filtering and spike suppression. 000: Fast/Standard mode, 50 kbit/s 001: Fast/Standard mode, 100 kbit/s 010: Fast/Standard mode, 200 kbit/s 011: Fast/Standard mode, 400 kbit/s 100: High-speed mode, 800 kbit/s 101: High-speed mode, 1.2 Mbit/s 110: High-speed mode, 1.7 Mbit/s 111: High-speed mode, 3.4 Mbit/s)
Definition at line 20578 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::nwr |
[0..0] Transfer direction (not-write/read): 0: cmd will be executed as write 1: cmd will be executed as read Master FIFO-requests (IRQ and DMA) are generated depending on this direction flag.
[21..21] Transfer direction detected after last (r)START. 0: The last start-byte defined a write transfer. 1: The last start-byte defined a read transfer. This read-only status bit is always reset to 0 during (r)START. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic. Note: This bit does not depend on whether the start-byte has been acknowledged or not.
Definition at line 20660 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::nwr_aced |
[25..25] Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing). 0: The last acknowledged start-byte defined a write transfer. 1: The last acknowledged start-byte defined a read transfer. Slave FIFO requests generating IRQ and DMA requests depend on this direction flag. This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Definition at line 20852 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::pio_mode |
[16..16] If this bit is set, SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C). In PIO mode, the I2C controller state machine is disabled: FIFOs are not used, no IRQs will be set, and no DMA controlling is possible.
Definition at line 20598 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::rst_i2c |
[17..17] Reset the I2C bus-state-detection logic. To avoid conflicts with other masters, some I2C bus states, which are important when there are multiple masters on the I2C bus, are always monitored, even if the I2C module is disabled. For details, see bits i2c_sr.started and i2c.bus_master. However, it may happen that bus states are detected which lock up the I2C module. E.g. hazards during power-up or IO configuration or sequences, which are not I2C compliant, can cause a lock-up. This bit can be used to escape f
Definition at line 20603 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sadr |
[10..4] 7-bit slave address sent after (r)START: For 10-bit addressing, the first byte (10-bit start '11110', address bits[9:8] must be programmed here. The second start byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr). This register must be rewritten (even if the value does not change) to address another slave in the 10-bit mode (run 2-byte start sequence). The register must not be rewritten before a repeated START on the same 10-bit addressed slave (run 1-byte start sequence e.g. write
Definition at line 20587 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::scl_in_ro |
[2..2] SCL input state (read-only)
Definition at line 21026 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::scl_oe |
[1..1] SCL output enable 0: Do not drive SCL, switch pad to high-z. 1: Drive SCL, switch pad to programmed scl_out-state
Definition at line 21024 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::scl_out |
[0..0] Driving level of SCL (1: high, 0: low) if output is enabled (scl_oe is set)
Definition at line 21022 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::scl_state |
[30..30] SCL signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit.
Definition at line 20889 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sda_in_ro |
[6..6] SDA input state (read-only)
Definition at line 21032 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sda_oe |
[5..5] SDA output enable 0: Do not drive SDA, switch pad to high-z. 1: Drive SDA, switch pad to programmed sda_out-state
Definition at line 21030 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sda_out |
[4..4] Driving level of SDA (1: high, 0: low) if output is enabled (sda_oe is set)
Definition at line 21028 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sda_state |
[31..31] SDA signal state sampled and filtered from bus (e.g. to detect bus blockings) This is a read-only status bit.
Definition at line 20891 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sdata |
[7..0] I2C slave transmit or receive data: The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START.
Definition at line 20735 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sdmab_en |
[3..3] Enable DMA burst requests for I2C slave data. The DMA controller must be the flow controller. This bit is writable, but can also be changed by hardware.
Definition at line 21001 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sdmas_en |
[2..2] Enable DMA single requests for I2C slave data. The DMA controller must be the flow controller. This bit is writable, but can also be changed by hardware.
Definition at line 20998 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_clr |
[8..8] Clear slave data FIFO, write only bit. This bit is writable, but can also be changed by hardware.
Definition at line 20771 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_empty |
[16..16] Slave FIFO is empty (1 if empty) This is a read-only status bit.
Definition at line 20799 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_err_ovfl |
[18..18] Slave FIFO overflow error occurred. Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
Definition at line 20803 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_err_undr |
[19..19] Slave FIFO underrun error occurred. Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
Definition at line 20807 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_full |
[17..17] Slave FIFO is full (1 if full) This is a read-only status bit.
Definition at line 20801 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_level |
[14..10] Slave FIFO level (0..16) This is a read-only status bit field.
Definition at line 20796 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_req |
[5..5] Slave FIFO action request interrupt mask
[5..5] Unmasked slave FIFO action request interrupt state: Purpose: Slave FIFO should be updated 1: Slave FIFO request: i2c_sr.sfifo_level is above or below i2c_sfifo_cr.sfifo_wm (see description i2c_sfifo_cr) 0: Slave FIFO state not critical
Definition at line 20911 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::sfifo_req |
[5..5] Masked slave FIFO action request interrupt state
Definition at line 20967 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sfifo_wm |
[3..0] Slave FIFO watermark for the generation of IRQ sfifo_req: If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave), IRQ sfifo_req is generated if sfifo_level<sfifo_wm. If the slave is not the transmitter (is receiver or not selected), IRQ sfifo_req is generated if sfifo_level>sfifo_wm.
Definition at line 20764 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sid |
[9..0] Slave device ID/address: External masters can address this device (this I2C module in slave mode) by the ID/address programmed here. If sid10 is not set, bits 9 to 7 will be ignored.
Definition at line 20624 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sid10 |
[10..10] 10-bit slave device ID/address: 0: Wait for 7-bit slave address after (r)START 1: Wait for 10-bit slave address after (r)START
Definition at line 20628 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sid10_aced |
[27..27] 10-bit slave address acknowledge state. { | 0: There was no 10-bit slave address or it was not acknowledged. 1: A 10-bit slave address was broadcasted and a slave acknowledged this broadcast. I.e. for the master side: A 10-bit slave was addressed and the slave acknowledged. I.e. for the slave side: A master broadcasted a start with the address programmed in register i2c_scr.sid and the i2c module acknowledged this broadcast as bit i2c_scr.ac_start is set.} This read-only status bit is cleared automaticall
Definition at line 20869 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::slave_access |
[23..23] Slave access state. 0: No slave access to this device. 1: A master addressed this slave device. This read-only status bit is set if a start-byte (2 bytes for 10-bit address) containing the address programmed in register i2c_scr.sid has been received. This bit is always reset to 0 during START or STOP. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic. Note: This bit does not depend on whether the start-byte has been acknowledged or not.
Definition at line 20838 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::sreq |
[6..6] Slave request interrupt mask
[6..6] Unmasked slave request interrupt state: Purpose: Set up slave FIFO 1: External master was running START-sequence and requested this slave 0: Slave is not requested
Definition at line 20912 of file netx90_app.h.
| __IM uint32_t i2c_app_Type::sreq |
[6..6] Masked slave request interrupt state
Definition at line 20968 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::started |
[22..22] START condition detection: 0: The bus is idle (STOP was detected, not started). 1: (r)START was detected on the bus. The bus is occupied. This detection will also take place while the module is disabled. This is important if there are multiple I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the I2C module must not start a transfer, before the other master has released the bus. Use bit i2c_mcr.rst_i2c to force this read-only status bit to '0', e.g. in order to es
Definition at line 20828 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::timeout |
[28..28] I2C command timeout detection (for I2C master). I2C slaves can stretch low SCL phases by holding the SCL line low. The master must detect this and wait until the SCL line is released before the current transfer can continue. In error cases, the I2C bus can be blocked permanently by a low signal state of SCL. The reason for the blocking can be e.g. a crashed I2C slave or a false I/O configuration. To escape from such a situation, a timeout watchdog is implemented: A timeout will be detected if the SCL line
Definition at line 20878 of file netx90_app.h.
| __IOM uint32_t i2c_app_Type::tsize |
[17..8] Transfer tsize+1 bytes (1...1024): If no acknowledge is generated by the slave (receiver), write transfers will be terminated and IRQ cmd_err will be generated. For 10-bit-addressing, the second start-byte (lower address bits) must be on top of the master FIFO. For subsequent transfers, the value programmed here has to ignore this byte. This value will count down during transfers after each byte. This bit is writable, but can also be changed by hardware.
Definition at line 20674 of file netx90_app.h.
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