pio_app_Type Struct Reference

pio_app (pio_app) More...

#include <netx90_app.h>

Collaboration diagram for pio_app_Type:

Data Fields
union {
__IM uint32_t   pio_in
struct {
__IM uint32_t   val: 29
__IM uint32_t   bf_align0: 3
}   pio_in_b
};
union {
__IOM uint32_t   pio_out
struct {
__IOM uint32_t   val: 29
__IOM uint32_t   bf_align0: 3
}   pio_out_b
};
union {
__IOM uint32_t   pio_oe
struct {
__IOM uint32_t   val: 29
__IOM uint32_t   bf_align0: 3
}   pio_oe_b
};
union {
__IM uint32_t   pio_io_link_in
struct {
__IM uint32_t   val: 8
__IM uint32_t   bf_align0: 24
}   pio_io_link_in_b
};
union {
__IOM uint32_t   pio_in_inv
struct {
__IOM uint32_t   val: 29
__IOM uint32_t   bf_align0: 3
}   pio_in_inv_b
};
union {
__IOM uint32_t   pio_edge_event
struct {
__IOM uint32_t   val: 29
__IOM uint32_t   bf_align0: 3
}   pio_edge_event_b
};
union {
__IOM uint32_t   pio_irq_raw
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq_raw_b
};
union {
__IM uint32_t   pio_irq0_masked
struct {
__IM uint32_t   pio: 29
__IM uint32_t   bf_align0: 3
}   pio_irq0_masked_b
};
union {
__IOM uint32_t   pio_irq0_msk_set
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq0_msk_set_b
};
union {
__IOM uint32_t   pio_irq0_msk_reset
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq0_msk_reset_b
};
union {
__IM uint32_t   pio_irq1_masked
struct {
__IM uint32_t   pio: 29
__IM uint32_t   bf_align0: 3
}   pio_irq1_masked_b
};
union {
__IOM uint32_t   pio_irq1_msk_set
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq1_msk_set_b
};
union {
__IOM uint32_t   pio_irq1_msk_reset
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq1_msk_reset_b
};
union {
__IM uint32_t   pio_irq2_masked
struct {
__IM uint32_t   pio: 29
__IM uint32_t   bf_align0: 3
}   pio_irq2_masked_b
};
union {
__IOM uint32_t   pio_irq2_msk_set
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq2_msk_set_b
};
union {
__IOM uint32_t   pio_irq2_msk_reset
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq2_msk_reset_b
};
union {
__IM uint32_t   pio_irq3_masked
struct {
__IM uint32_t   pio: 29
__IM uint32_t   bf_align0: 3
}   pio_irq3_masked_b
};
union {
__IOM uint32_t   pio_irq3_msk_set
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq3_msk_set_b
};
union {
__IOM uint32_t   pio_irq3_msk_reset
struct {
__IOM uint32_t   pio: 29
__IOM uint32_t   bf_align0: 3
}   pio_irq3_msk_reset_b
};

Detailed Description

pio_app (pio_app)

Definition at line 24908 of file netx90_app.h.

Field Documentation

union { ... }

< (@ 0xFF801500) pio_app Structure

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__IM uint32_t pio_app_Type::bf_align0

[31..29] bitField alignment value for aeabi compatibility

[31..8] bitField alignment value for aeabi compatibility

Definition at line 24917 of file netx90_app.h.

__IOM uint32_t pio_app_Type::bf_align0

[31..29] bitField alignment value for aeabi compatibility

Definition at line 24928 of file netx90_app.h.

__IOM uint32_t pio_app_Type::pio

[28..0] event or active level at PIO input

Definition at line 24992 of file netx90_app.h.

__IM uint32_t pio_app_Type::pio

[28..0] event or active level at PIO input

Definition at line 25002 of file netx90_app.h.

__IOM uint32_t pio_app_Type::pio_edge_event

(@ 0x00000014) generate IRQ at edge of PIO, otherwise level.

Definition at line 24973 of file netx90_app.h.

struct { ... } pio_app_Type::pio_edge_event_b

__IM uint32_t pio_app_Type::pio_in

(@ 0x00000000) PIO input line status register. Each PIO input status can also be read from dedicated PIOx input state register.

Definition at line 24911 of file netx90_app.h.

struct { ... } pio_app_Type::pio_in_b

__IOM uint32_t pio_app_Type::pio_in_inv

(@ 0x00000010) Invert input of PIO.

Definition at line 24964 of file netx90_app.h.

struct { ... } pio_app_Type::pio_in_inv_b

__IM uint32_t pio_app_Type::pio_io_link_in

(@ 0x0000000C) IO-Link input values. This register collects the inputs of 8 IO-Link ports for use in IO-Link IO-mode. In this mode the output and output-enable values are set by PIO pins independant on xPIC or IO-Link module. The relation of IO-Link-pin and PIO-pin can be seen in the global netX90 pinning sheet: io_link7_out->pio27, io_link7_oe->pio28 io_link6_out->pio24, io_link6_oe->pio25 io_link5_out->pio22, io_link5_oe->pio23 io_link4_out->pio19, io_link4_oe->pio21 io_link3_out->pio14, io

Definition at line 24944 of file netx90_app.h.

struct { ... } pio_app_Type::pio_io_link_in_b

__IM uint32_t pio_app_Type::pio_irq0_masked

(@ 0x0000001C) Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC).

Definition at line 24998 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq0_masked_b

__IOM uint32_t pio_app_Type::pio_irq0_msk_reset

(@ 0x00000024) IRQ disable mask: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit.

Definition at line 25027 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq0_msk_reset_b

__IOM uint32_t pio_app_Type::pio_irq0_msk_set

(@ 0x00000020) IRQ enable mask: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.

Definition at line 25008 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq0_msk_set_b

__IM uint32_t pio_app_Type::pio_irq1_masked

(@ 0x00000028) Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC).

Definition at line 25040 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq1_masked_b

__IOM uint32_t pio_app_Type::pio_irq1_msk_reset

(@ 0x00000030) IRQ disable mask: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit.

Definition at line 25069 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq1_msk_reset_b

__IOM uint32_t pio_app_Type::pio_irq1_msk_set

(@ 0x0000002C) IRQ enable mask: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.

Definition at line 25050 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq1_msk_set_b

__IM uint32_t pio_app_Type::pio_irq2_masked

(@ 0x00000034) Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC).

Definition at line 25082 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq2_masked_b

__IOM uint32_t pio_app_Type::pio_irq2_msk_reset

(@ 0x0000003C) IRQ disable mask: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit.

Definition at line 25111 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq2_msk_reset_b

__IOM uint32_t pio_app_Type::pio_irq2_msk_set

(@ 0x00000038) IRQ enable mask: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.

Definition at line 25092 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq2_msk_set_b

__IM uint32_t pio_app_Type::pio_irq3_masked

(@ 0x00000040) Masked IRQ: Shows status of masked IRQs (as connected to ARM/xPIC).

Definition at line 25124 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq3_masked_b

__IOM uint32_t pio_app_Type::pio_irq3_msk_reset

(@ 0x00000048) IRQ disable mask: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit.

Definition at line 25153 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq3_msk_reset_b

__IOM uint32_t pio_app_Type::pio_irq3_msk_set

(@ 0x00000044) IRQ enable mask: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_pio_irq_raw.

Definition at line 25134 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq3_msk_set_b

__IOM uint32_t pio_app_Type::pio_irq_raw

(@ 0x00000018) Raw IRQ: Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source). Write access with '0' does not influence this bit.

Definition at line 24983 of file netx90_app.h.

struct { ... } pio_app_Type::pio_irq_raw_b

__IOM uint32_t pio_app_Type::pio_oe

(@ 0x00000008) PIO output enable line register. Each PIOs output enable can also be programmed by dedicated PIOx output enable register.

Definition at line 24933 of file netx90_app.h.

struct { ... } pio_app_Type::pio_oe_b

__IOM uint32_t pio_app_Type::pio_out

(@ 0x00000004) PIO output drive level line register. Each PIOs output drive level can also be programmed by dedicated PIOx output drive level register.

Definition at line 24922 of file netx90_app.h.

struct { ... } pio_app_Type::pio_out_b

__IM uint32_t pio_app_Type::val

[28..0] PIO input states (LSB: PIO0).

[7..0] IO-Link input

Definition at line 24916 of file netx90_app.h.

__IOM uint32_t pio_app_Type::val

[28..0] PIO output drive levels (LSB: PIO0).

[28..0] PIO output enables (LSB: PIO0).

[28..0] Invert PIO

[28..0] Edge detect 0: generate IRQ if (inverted) PIO is high level 1: generate IRQ at rising edge of (inverted) PIO

Definition at line 24927 of file netx90_app.h.

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The documentation for this struct was generated from the following file:

• netx90_app.h