Hilscher netX microcontroller driver  V0.0.5.0
Documentation of the netX driver package
Data Structures | Macros | Typedefs | Enumerations
netX90 Final Silicon
netX90 Application Side Drivers » Chip Support Package
Collaboration diagram for netX90 Final Silicon:

Data Structures

union  DRV_SPI_DEVICE_U
 

Macros

#define DRV_CORTEX_MODULE_SUPPORTED
 
#define DRV_BISS_MODULE_SUPPORTED
 
#define DRV_CANCTRL_MODULE_SUPPORTED
 
#define DRV_XPIC_MODULE_SUPPORTED
 
#define DRV_ETH_XPIC_MODULE_SUPPORTED
 
#define DRV_ASIC_CTRL_DEVICE   ((DRV_ASIC_CTRL_T*) asic_ctrl_BASE)
 
#define DRV_MLED_MODULE_SUPPORTED
 
#define DRV_MLED_DEVICE   ((DRV_MLED_DEVICE_T*) mled_ctrl_app_BASE)
 
#define DRV_MLED_DEVICE_COUNT   1
 
#define DRV_MLED_DEVICE_LIST   { DRV_MLED_DEVICE }
 
#define DRV_MLED_MSK_0   (uint32_t)0x00000001ull
 
#define DRV_MLED_MSK_1   (uint32_t)0x00000002ull
 
#define DRV_MLED_MSK_2   (uint32_t)0x00000004ull
 
#define DRV_MLED_MSK_3   (uint32_t)0x00000008ull
 
#define DRV_MLED_MSK_4   (uint32_t)0x00000010ull
 
#define DRV_MLED_MSK_5   (uint32_t)0x00000020ull
 
#define DRV_MLED_MSK_6   (uint32_t)0x00000040ull
 
#define DRV_MLED_MSK_7   (uint32_t)0x00000080ull
 
#define DRV_MLED_MSK_8   (uint32_t)0x00000100ull
 
#define DRV_MLED_MSK_9   (uint32_t)0x00000200ull
 
#define DRV_MLED_MSK_10   (uint32_t)0x00000400ull
 
#define DRV_MLED_MSK_11   (uint32_t)0x00000800ull
 
#define DRV_MLED_MSK_12   (uint32_t)0x00001000ull
 
#define DRV_MLED_MSK_13   (uint32_t)0x00002000ull
 
#define DRV_MLED_MSK_14   (uint32_t)0x00004000ull
 
#define DRV_MLED_MSK_15   (uint32_t)0x00008000ull
 
#define DRV_MLED_LINE_MSK   (uint32_t)0x0000FFFFull
 
#define DRV_MLED_ID_MIN   DRV_MLED_ID_0
 
#define DRV_MLED_ID_0   0x000000u
 
#define DRV_MLED_ID_1   0x000001u
 
#define DRV_MLED_ID_2   0x000002u
 
#define DRV_MLED_ID_3   0x000003u
 
#define DRV_MLED_ID_4   0x000004u
 
#define DRV_MLED_ID_5   0x000005u
 
#define DRV_MLED_ID_6   0x000006u
 
#define DRV_MLED_ID_7   0x000007u
 
#define DRV_MLED_ID_8   0x000008u
 
#define DRV_MLED_ID_9   0x000009u
 
#define DRV_MLED_ID_10   0x00000au
 
#define DRV_MLED_ID_11   0x00000bu
 
#define DRV_MLED_ID_12   0x00000cu
 
#define DRV_MLED_ID_13   0x00000du
 
#define DRV_MLED_ID_14   0x00000eu
 
#define DRV_MLED_ID_15   0x00000fu
 
#define DRV_MLED_ID_MAX   DRV_MLED_ID_15
 
#define DRV_DIO_MODULE_SUPPORTED
 
#define DRV_MMIO_DEVICE   ((DRV_MMIO_DEVICE_T*) mmio_ctrl_BASE)
 
#define DRV_HIF_IO_DEVICE   ((DRV_HIF_IO_DEVICE_T*) hif_io_ctrl_BASE)
 
#define DRV_GPIO_DEVICE   ((DRV_GPIO_DEVICE_T*) gpio_app_BASE)
 
#define DRV_GPIO_XPIC_DEVICE   ((DRV_GPIO_DEVICE_T*) gpio_xpic_app_BASE)
 
#define DRV_PIO_DEVICE   ((DRV_PIO_DEVICE_T*) pio_app_BASE)
 
#define DRV_DIO_PIO_INVERT_SUPPORTED
 
#define DRV_DIO_PIO_IRQ_SUPPORTED
 
#define DRV_GPIO_IRQ_COUNT   8
 
#define DRV_GPIO_IRQ_LIST   gpio_app0_IRQn, gpio_app1_IRQn, gpio_app2_IRQn, gpio_app3_IRQn, gpio_app4_IRQn, gpio_app5_IRQn, gpio_app6_IRQn, gpio_app7_IRQn
 
#define DRV_GPIO0_IRQ   gpio_app0_IRQn
 
#define DRV_HIF_IRQ_COUNT   4
 
#define DRV_HIFPIO_IRQ   hif_pio_arm_IRQn
 
#define DRV_PIO_IRQ_COUNT   29
 
#define DRV_PIO_IRQ   pio0_app_IRQn
 
#define DRV_BOD_IRQ   bod_IRQn
 
#define DRV_BOD_IRQ_COUNT   1
 
#define DRV_DIO_IRQ_COUNT   DRV_GPIO_IRQ_COUNT + DRV_HIF_IRQ_COUNT + DRV_BOD_IRQ_COUNT + DRV_PIO_IRQ_COUNT
 
#define DRV_DIO_LINE_MSK_NONE   (uint64_t)0x0000000000000000ull
 
#define DRV_DIO_LINE_MSK_GPIO   (uint64_t)0x00000000000000FFull
 
#define DRV_DIO_LINE_MSK_PIO   (uint64_t)0x000000001FFFFFFFull
 
#define DRV_DIO_LINE_MSK_MMIO   (uint64_t)0x00000000000000FFull
 
#define DRV_DIO_LINE_MSK_HIF   (uint64_t)0xFE03FFFF0000FFFFull
 
#define DRV_DIO_MSK_GPIO_0   (uint64_t)0x0000000000000001ull
 
#define DRV_DIO_MSK_GPIO_1   (uint64_t)0x0000000000000002ull
 
#define DRV_DIO_MSK_GPIO_2   (uint64_t)0x0000000000000004ull
 
#define DRV_DIO_MSK_GPIO_3   (uint64_t)0x0000000000000008ull
 
#define DRV_DIO_MSK_GPIO_4   (uint64_t)0x0000000000000010ull
 
#define DRV_DIO_MSK_GPIO_5   (uint64_t)0x0000000000000020ull
 
#define DRV_DIO_MSK_GPIO_6   (uint64_t)0x0000000000000040ull
 
#define DRV_DIO_MSK_GPIO_7   (uint64_t)0x0000000000000080ull
 
#define DRV_DIO_MSK_PIO_0   (uint64_t)0x0000000000000001ull
 
#define DRV_DIO_MSK_PIO_1   (uint64_t)0x0000000000000002ull
 
#define DRV_DIO_MSK_PIO_2   (uint64_t)0x0000000000000004ull
 
#define DRV_DIO_MSK_PIO_3   (uint64_t)0x0000000000000008ull
 
#define DRV_DIO_MSK_PIO_4   (uint64_t)0x0000000000000010ull
 
#define DRV_DIO_MSK_PIO_5   (uint64_t)0x0000000000000020ull
 
#define DRV_DIO_MSK_PIO_6   (uint64_t)0x0000000000000040ull
 
#define DRV_DIO_MSK_PIO_7   (uint64_t)0x0000000000000080ull
 
#define DRV_DIO_MSK_PIO_8   (uint64_t)0x0000000000000100ull
 
#define DRV_DIO_MSK_PIO_9   (uint64_t)0x0000000000000200ull
 
#define DRV_DIO_MSK_PIO_10   (uint64_t)0x0000000000000400ull
 
#define DRV_DIO_MSK_PIO_11   (uint64_t)0x0000000000000800ull
 
#define DRV_DIO_MSK_PIO_12   (uint64_t)0x0000000000001000ull
 
#define DRV_DIO_MSK_PIO_13   (uint64_t)0x0000000000002000ull
 
#define DRV_DIO_MSK_PIO_14   (uint64_t)0x0000000000004000ull
 
#define DRV_DIO_MSK_PIO_15   (uint64_t)0x0000000000008000ull
 
#define DRV_DIO_MSK_PIO_16   (uint64_t)0x0000000000010000ull
 
#define DRV_DIO_MSK_PIO_17   (uint64_t)0x0000000000020000ull
 
#define DRV_DIO_MSK_PIO_18   (uint64_t)0x0000000000040000ull
 
#define DRV_DIO_MSK_PIO_19   (uint64_t)0x0000000000080000ull
 
#define DRV_DIO_MSK_PIO_20   (uint64_t)0x0000000000100000ull
 
#define DRV_DIO_MSK_PIO_21   (uint64_t)0x0000000000200000ull
 
#define DRV_DIO_MSK_PIO_22   (uint64_t)0x0000000000400000ull
 
#define DRV_DIO_MSK_PIO_23   (uint64_t)0x0000000000800000ull
 
#define DRV_DIO_MSK_PIO_24   (uint64_t)0x0000000001000000ull
 
#define DRV_DIO_MSK_PIO_25   (uint64_t)0x0000000002000000ull
 
#define DRV_DIO_MSK_PIO_26   (uint64_t)0x0000000004000000ull
 
#define DRV_DIO_MSK_PIO_27   (uint64_t)0x0000000008000000ull
 
#define DRV_DIO_MSK_PIO_28   (uint64_t)0x0000000010000000ull
 
#define DRV_DIO_MSK_MMIO_0   (uint64_t)0x0000000000000001ull
 
#define DRV_DIO_MSK_MMIO_1   (uint64_t)0x0000000000000002ull
 
#define DRV_DIO_MSK_MMIO_2   (uint64_t)0x0000000000000004ull
 
#define DRV_DIO_MSK_MMIO_3   (uint64_t)0x0000000000000008ull
 
#define DRV_DIO_MSK_MMIO_4   (uint64_t)0x0000000000000010ull
 
#define DRV_DIO_MSK_MMIO_5   (uint64_t)0x0000000000000020ull
 
#define DRV_DIO_MSK_MMIO_6   (uint64_t)0x0000000000000040ull
 
#define DRV_DIO_MSK_MMIO_7   (uint64_t)0x0000000000000080ull
 
#define DRV_DIO_MSK_HIF_D0   (uint64_t)0x0000000000000001ull
 
#define DRV_DIO_MSK_HIF_D1   (uint64_t)0x0000000000000002ull
 
#define DRV_DIO_MSK_HIF_D2   (uint64_t)0x0000000000000004ull
 
#define DRV_DIO_MSK_HIF_D3   (uint64_t)0x0000000000000008ull
 
#define DRV_DIO_MSK_HIF_D4   (uint64_t)0x0000000000000010ull
 
#define DRV_DIO_MSK_HIF_D5   (uint64_t)0x0000000000000020ull
 
#define DRV_DIO_MSK_HIF_D6   (uint64_t)0x0000000000000040ull
 
#define DRV_DIO_MSK_HIF_D7   (uint64_t)0x0000000000000080ull
 
#define DRV_DIO_MSK_HIF_D8   (uint64_t)0x0000000000000100ull
 
#define DRV_DIO_MSK_HIF_D9   (uint64_t)0x0000000000000200ull
 
#define DRV_DIO_MSK_HIF_D10   (uint64_t)0x0000000000000400ull
 
#define DRV_DIO_MSK_HIF_D11   (uint64_t)0x0000000000000800ull
 
#define DRV_DIO_MSK_HIF_D12   (uint64_t)0x0000000000001000ull
 
#define DRV_DIO_MSK_HIF_D13   (uint64_t)0x0000000000002000ull
 
#define DRV_DIO_MSK_HIF_D14   (uint64_t)0x0000000000004000ull
 
#define DRV_DIO_MSK_HIF_D15   (uint64_t)0x0000000000008000ull
 
#define DRV_DIO_MSK_HIF_D_RESERVED   (uint64_t)0x00000000FFFF0000ull
 
#define DRV_DIO_MSK_HIF_A0   (uint64_t)0x0000000100000000ull
 
#define DRV_DIO_MSK_HIF_A1   (uint64_t)0x0000000200000000ull
 
#define DRV_DIO_MSK_HIF_A2   (uint64_t)0x0000000400000000ull
 
#define DRV_DIO_MSK_HIF_A3   (uint64_t)0x0000000800000000ull
 
#define DRV_DIO_MSK_HIF_A4   (uint64_t)0x0000001000000000ull
 
#define DRV_DIO_MSK_HIF_A5   (uint64_t)0x0000002000000000ull
 
#define DRV_DIO_MSK_HIF_A6   (uint64_t)0x0000004000000000ull
 
#define DRV_DIO_MSK_HIF_A7   (uint64_t)0x0000008000000000ull
 
#define DRV_DIO_MSK_HIF_A8   (uint64_t)0x0000010000000000ull
 
#define DRV_DIO_MSK_HIF_A9   (uint64_t)0x0000020000000000ull
 
#define DRV_DIO_MSK_HIF_A10   (uint64_t)0x0000040000000000ull
 
#define DRV_DIO_MSK_HIF_A11   (uint64_t)0x0000080000000000ull
 
#define DRV_DIO_MSK_HIF_A12   (uint64_t)0x0000100000000000ull
 
#define DRV_DIO_MSK_HIF_A13   (uint64_t)0x0000200000000000ull
 
#define DRV_DIO_MSK_HIF_A14   (uint64_t)0x0000400000000000ull
 
#define DRV_DIO_MSK_HIF_A15   (uint64_t)0x0000800000000000ull
 
#define DRV_DIO_MSK_HIF_A16   (uint64_t)0x0001000000000000ull
 
#define DRV_DIO_MSK_HIF_A17   (uint64_t)0x0002000000000000ull
 
#define DRV_DIO_MSK_HIF_A_RESERVED   (uint64_t)0x01fc000000000000ull
 
#define DRV_DIO_MSK_HIF_BHEN   (uint64_t)0x0200000000000000ull
 
#define DRV_DIO_MSK_HIF_RDN   (uint64_t)0x0400000000000000ull
 
#define DRV_DIO_MSK_HIF_WRN   (uint64_t)0x0800000000000000ull
 
#define DRV_DIO_MSK_HIF_CSN   (uint64_t)0x1000000000000000ull
 
#define DRV_DIO_MSK_HIF_RDY   (uint64_t)0x2000000000000000ull
 
#define DRV_DIO_MSK_HIF_DIRQ   (uint64_t)0x4000000000000000ull
 
#define DRV_DIO_MSK_HIF_SDCLK   (uint64_t)0x8000000000000000ull
 
#define DRV_DIO_ID_GPIO_MIN   DRV_DIO_ID_GPIO_0
 
#define DRV_DIO_ID_GPIO_0   0x100000u
 
#define DRV_DIO_ID_GPIO_1   0x100001u
 
#define DRV_DIO_ID_GPIO_2   0x100002u
 
#define DRV_DIO_ID_GPIO_3   0x100003u
 
#define DRV_DIO_ID_GPIO_4   0x100004u
 
#define DRV_DIO_ID_GPIO_5   0x100005u
 
#define DRV_DIO_ID_GPIO_6   0x100006u
 
#define DRV_DIO_ID_GPIO_7   0x100007u
 
#define DRV_DIO_ID_GPIO_MAX   DRV_DIO_ID_GPIO_7
 
#define DRV_DIO_ID_PIO_MIN   DRV_DIO_ID_PIO_0
 
#define DRV_DIO_ID_PIO_0   0x200000u
 
#define DRV_DIO_ID_PIO_1   0x200001u
 
#define DRV_DIO_ID_PIO_2   0x200002u
 
#define DRV_DIO_ID_PIO_3   0x200003u
 
#define DRV_DIO_ID_PIO_4   0x200004u
 
#define DRV_DIO_ID_PIO_5   0x200005u
 
#define DRV_DIO_ID_PIO_6   0x200006u
 
#define DRV_DIO_ID_PIO_7   0x200007u
 
#define DRV_DIO_ID_PIO_8   0x200008u
 
#define DRV_DIO_ID_PIO_9   0x200009u
 
#define DRV_DIO_ID_PIO_10   0x20000au
 
#define DRV_DIO_ID_PIO_11   0x20000bu
 
#define DRV_DIO_ID_PIO_12   0x20000cu
 
#define DRV_DIO_ID_PIO_13   0x20000du
 
#define DRV_DIO_ID_PIO_14   0x20000eu
 
#define DRV_DIO_ID_PIO_15   0x20000fu
 
#define DRV_DIO_ID_PIO_16   0x200010u
 
#define DRV_DIO_ID_PIO_17   0x200011u
 
#define DRV_DIO_ID_PIO_18   0x200012u
 
#define DRV_DIO_ID_PIO_19   0x200013u
 
#define DRV_DIO_ID_PIO_20   0x200014u
 
#define DRV_DIO_ID_PIO_21   0x200015u
 
#define DRV_DIO_ID_PIO_22   0x200016u
 
#define DRV_DIO_ID_PIO_23   0x200017u
 
#define DRV_DIO_ID_PIO_24   0x200018u
 
#define DRV_DIO_ID_PIO_25   0x200019u
 
#define DRV_DIO_ID_PIO_26   0x20001au
 
#define DRV_DIO_ID_PIO_27   0x20001bu
 
#define DRV_DIO_ID_PIO_28   0x20001cu
 
#define DRV_DIO_ID_PIO_MAX   DRV_DIO_ID_PIO_28
 
#define DRV_DIO_ID_MMIO_MIN   DRV_DIO_ID_MMIO_0
 
#define DRV_DIO_ID_MMIO_0   0x300000u
 
#define DRV_DIO_ID_MMIO_1   0x300001u
 
#define DRV_DIO_ID_MMIO_2   0x300002u
 
#define DRV_DIO_ID_MMIO_3   0x300003u
 
#define DRV_DIO_ID_MMIO_4   0x300004u
 
#define DRV_DIO_ID_MMIO_5   0x300005u
 
#define DRV_DIO_ID_MMIO_6   0x300006u
 
#define DRV_DIO_ID_MMIO_7   0x300007u
 
#define DRV_DIO_ID_MMIO_MAX   DRV_DIO_ID_MMIO_7
 
#define DRV_DIO_ID_HIF_MIN   DRV_DIO_ID_HIF_D0
 
#define DRV_DIO_ID_HIF_D0   0x400000u
 
#define DRV_DIO_ID_HIF_D1   0x400001u
 
#define DRV_DIO_ID_HIF_D2   0x400002u
 
#define DRV_DIO_ID_HIF_D3   0x400003u
 
#define DRV_DIO_ID_HIF_D4   0x400004u
 
#define DRV_DIO_ID_HIF_D5   0x400005u
 
#define DRV_DIO_ID_HIF_D6   0x400006u
 
#define DRV_DIO_ID_HIF_D7   0x400007u
 
#define DRV_DIO_ID_HIF_D8   0x400008u
 
#define DRV_DIO_ID_HIF_D9   0x400009u
 
#define DRV_DIO_ID_HIF_D10   0x40000au
 
#define DRV_DIO_ID_HIF_D11   0x40000bu
 
#define DRV_DIO_ID_HIF_D12   0x40000cu
 
#define DRV_DIO_ID_HIF_D13   0x40000du
 
#define DRV_DIO_ID_HIF_D14   0x40000eu
 
#define DRV_DIO_ID_HIF_D15   0x40000fu
 
#define DRV_DIO_ID_HIF_RESERVED0
 
#define DRV_DIO_ID_HIF_A0   0x400020u
 
#define DRV_DIO_ID_HIF_A1   0x400021u
 
#define DRV_DIO_ID_HIF_A2   0x400022u
 
#define DRV_DIO_ID_HIF_A3   0x400023u
 
#define DRV_DIO_ID_HIF_A4   0x400024u
 
#define DRV_DIO_ID_HIF_A5   0x400025u
 
#define DRV_DIO_ID_HIF_A6   0x400026u
 
#define DRV_DIO_ID_HIF_A7   0x400027u
 
#define DRV_DIO_ID_HIF_A8   0x400028u
 
#define DRV_DIO_ID_HIF_A9   0x400029u
 
#define DRV_DIO_ID_HIF_A10   0x40002au
 
#define DRV_DIO_ID_HIF_A11   0x40002bu
 
#define DRV_DIO_ID_HIF_A12   0x40002cu
 
#define DRV_DIO_ID_HIF_A13   0x40002du
 
#define DRV_DIO_ID_HIF_A14   0x40002eu
 
#define DRV_DIO_ID_HIF_A15   0x40002fu
 
#define DRV_DIO_ID_HIF_A16   0x400030u
 
#define DRV_DIO_ID_HIF_A17   0x400031u
 
#define DRV_DIO_ID_HIF_RESERVED1
 
#define DRV_DIO_ID_HIF_BHEN   0x400039u
 
#define DRV_DIO_ID_HIF_RDN   0x40003au
 
#define DRV_DIO_ID_HIF_WRN   0x40003bu
 
#define DRV_DIO_ID_HIF_CSN   0x40003cu
 
#define DRV_DIO_ID_HIF_RDY   0x40003du
 
#define DRV_DIO_ID_HIF_DIRQ   0x40003eu
 
#define DRV_DIO_ID_HIF_SDCLK   0x40003fu
 
#define DRV_DIO_ID_HIF_MAX   DRV_DIO_ID_HIF_SDCLK
 
#define DRV_DIO_ID_BOD   0x500070u
 
#define DRV_TIM_MODULE_SUPPORTED
 
#define DRV_TIMER_DEVICE   ((DRV_TIMER_DEVICE_T*) timer_app_BASE)
 
#define DRV_TIMER_XPIC_DEVICE   ((DRV_TIMER_DEVICE_T*) timer_xpic_app_BASE)
 
#define DRV_SYSTIME_LT_DEVICE   ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_app_BASE)
 
#define DRV_SYSTIME_LT_XPIC_DEVICE   ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_xpic_app_BASE)
 
#define DRV_SYSTIME_DEVICE   ((systime_app_Type*) systime_app_BASE)
 
#define DRV_GPIO_COUNTER_IRQs   gpio_app_timer0_IRQn, gpio_app_timer1_IRQn, gpio_app_timer2_IRQn
 
#define DRV_TIMER_IRQs   timer_app0_IRQn, timer_app1_IRQn, timer_app2_IRQn
 
#define DRV_SYSTIME_COMPARE_IRQ   timer_app_systime_s_IRQn
 
#define DRV_SYSTICK_IRQ   SysTick_IRQn
 
#define DRV_TIM_IRQ_COUNT   8u
 
#define DRV_TIM_IRQ_LIST   { DRV_GPIO_COUNTER_IRQs, DRV_TIMER_IRQs, DRV_SYSTIME_COMPARE_IRQ, DRV_SYSTICK_IRQ }
 
#define DRV_DMAC_MODULE_SUPPORTED
 
#define DMAC_APP_CH0_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE)
 
#define DMAC_APP_CH1_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+1)
 
#define DMAC_APP_CH2_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+2)
 
#define DMAC_APP_CH3_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+3)
 
#define DRV_DMAC_CH_DEVICE_COUNT   4
 
#define DRV_DMAC_REG_IRQ   dmac_app_IRQn
 
#define DRV_DMAC_CH_DEVICE_LIST   { DMAC_APP_CH0_DEVICE, DMAC_APP_CH1_DEVICE, DMAC_APP_CH2_DEVICE, DMAC_APP_CH3_DEVICE }
 
#define DMAC_APP_REG_DEVICE   ((DRV_DMAC_REG_DEVICE_T*) dmac_app_reg_BASE)
 
#define DMAC_MUX_APP_DEVICE   ((DRV_DMAC_MUX_DEVICE_T*) dmac_mux_app_BASE)
 
#define DRV_UART_MODULE_SUPPORTED
 
#define UART_DEVICE_SHARED   ((DRV_UART_DEVICE_T*) uart_BASE)
 
#define DRV_UART_IRQ_HANDLER0   UARTAPP_IRQHandler
 
#define UART_DEVICE_APP   ((DRV_UART_DEVICE_T*) uart_app_BASE)
 
#define DRV_UART_IRQ_HANDLER1   UARTXPIC_IRQHandler
 
#define UART_DEVICE_XPIC_APP   ((DRV_UART_DEVICE_T*) uart_xpic_app_BASE)
 
#define DRV_UART_IRQ_HANDLER2   UART_IRQHandler
 
#define DRV_UART_DEVICE_COUNT   3
 
#define DRV_UART_DEVICE_LIST   { UART_DEVICE_APP, UART_DEVICE_XPIC_APP, UART_DEVICE_SHARED }
 
#define DRV_UART_DEVICE_IRQ_LIST   { uart_app_IRQn, uart_xpic_app_IRQn, uart_IRQn }
 
#define DRV_UART_DEVICE_DMA_LIST   { DRV_DMAC_PERIPHERAL_UART_APP_RX, DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_UART_SHARED_RX }
 
#define DRV_SPI_MODULE_SUPPORTED
 
#define SPI_DEVICE_APP0   ((DRV_SPI_DEVICE_T*) spi0_app_BASE)
 
#define SPI_DEVICE_APP1   ((DRV_SPI_DEVICE_T*) spi1_app_BASE)
 
#define SPI_DEVICE_APP2   ((DRV_SPI_DEVICE_T*) spi2_app_BASE)
 
#define SPI_DEVICE_APP3   ((DRV_SPI_DEVICE_T*) spi_xpic_app_BASE)
 
#define SQI_DEVICE_SHARED   ((DRV_SQI_DEVICE_T*) sqi_BASE)
 
#define SQI_DEVICE_APP0   ((DRV_SQI_DEVICE_T*) sqi0_app_BASE)
 
#define SQI_DEVICE_APP1   ((DRV_SQI_DEVICE_T*) sqi1_app_BASE)
 
#define DRV_SPI_DEVICE_COUNT   7
 
#define DRV_SPI_DEVICE_LIST   { {(uintptr_t) SPI_DEVICE_APP0}, {(uintptr_t) SPI_DEVICE_APP1}, {(uintptr_t) SPI_DEVICE_APP2}, {(uintptr_t) SPI_DEVICE_APP3}, {(uintptr_t) SQI_DEVICE_SHARED}, {(uintptr_t) SQI_DEVICE_APP0}, {(uintptr_t) SQI_DEVICE_APP1}}
 
#define DRV_SPI_DEVICE_IRQ_LIST   { spi0_app_IRQn, spi1_app_IRQn, spi2_app_IRQn, spi_xpic_app_IRQn, sqi_IRQn, sqi0_app_IRQn, sqi1_app_IRQn }
 
#define DRV_SPI_DEVICE_DMA_LIST   { DRV_DMAC_PERIPHERAL_SPI0_APP_RX, DRV_DMAC_PERIPHERAL_SPI1_APP_RX, DRV_DMAC_PERIPHERAL_SPI2_APP_RX, DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_SQI_RX, DRV_DMAC_PERIPHERAL_SQI0_APP_RX, DRV_DMAC_PERIPHERAL_SQI1_APP_RX }
 
#define DRV_I2C_MODULE_SUPPORTED
 
#define I2C_DEVICE_APP0   ((DRV_I2C_DEVICE_T*) i2c_app_BASE)
 
#define DRV_I2C_IRQ_HANDLER0   I2C_IRQHandler
 
#define I2C_DEVICE_APP1   ((DRV_I2C_DEVICE_T*) i2c_xpic_app_BASE)
 
#define DRV_I2C_IRQ_HANDLER1   I2CXPIC_IRQHandler
 
#define DRV_I2C_DEVICE_COUNT   2
 
#define DRV_I2C_DEVICE_LIST   { I2C_DEVICE_APP0, I2C_DEVICE_APP1 }
 
#define DRV_I2C_DEVICE_IRQ_LIST   { i2c_app_IRQn, i2c_xpic_app_IRQn }
 
#define ADC_APP_DEVICE   ((DRV_ADC_DEVICE_T*) madc_BASE)
 
#define ADC_SEQ0_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq0_BASE)
 
#define ADC_SEQ1_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq1_BASE)
 
#define ADC_SEQ2_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq2_BASE)
 
#define ADC_SEQ3_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq3_BASE)
 
#define DRV_ADC_DEVICE_COUNT   1
 
#define DRV_ADC_DEVICE_LIST   { ADC_APP_DEVICE }
 
#define DRV_ADC_SEQ_DEVICE_COUNT   4
 
#define DRV_ADC_SEQ_DEVICE_LIST   { ADC_SEQ0_APP_DEVICE, ADC_SEQ1_APP_DEVICE, ADC_SEQ2_APP_DEVICE, ADC_SEQ3_APP_DEVICE }
 
#define DRV_ADC_SEQ_DEVICE_IRQ_LIST   { madc_seq0_IRQn, madc_seq1_IRQn, madc_seq2_IRQn, madc_seq3_IRQn }
 
#define DRV_ADC_COUNT   4
 
#define DRV_ADC_INPUTS_MAX   8
 
#define DRV_ADC_MEASUREMENTS_MAX   8
 
#define DRV_ADC_INPUT_COUNT01   4
 
#define DRV_ADC_INPUT_COUNT23   8
 
#define DRV_ADC_MODULE_SUPPORTED
 

Typedefs

typedef asic_ctrl_Type DRV_ASIC_CTRL_T
 
typedef mled_ctrl_app_Type DRV_MLED_DEVICE_T
 
typedef mmio_ctrl_Type DRV_MMIO_DEVICE_T
 
typedef hif_io_ctrl_Type DRV_HIF_IO_DEVICE_T
 
typedef gpio_app_Type DRV_GPIO_DEVICE_T
 
typedef pio_app_Type DRV_PIO_DEVICE_T
 
typedef timer_app_Type DRV_TIMER_DEVICE_T
 
typedef systime_lt_app_Type DRV_SYSTIME_LT_DEVICE_T
 
typedef systime_app_Type DRV_SYSTIME_DEVICE_T
 
typedef dmac_app_ch_Type DRV_DMAC_CH_DEVICE_T
 
typedef dmac_app_reg_Type DRV_DMAC_REG_DEVICE_T
 
typedef dmac_mux_app_Type DRV_DMAC_MUX_DEVICE_T
 
typedef uart_app_Type DRV_UART_DEVICE_T
 
typedef spi0_app_Type DRV_SPI_DEVICE_T
 
typedef sqi_Type DRV_SQI_DEVICE_T
 
typedef i2c_app_Type DRV_I2C_DEVICE_T
 
typedef madc_Type DRV_ADC_DEVICE_T
 
typedef madc_seq0_Type DRV_ADC_SEQ_DEVICE_T
 

Enumerations

enum  DRV_TIM_DEVICE_ID_E {
  DRV_TIM_DEVICE_ID_GPIOCNTR0 = 0x10ul,
  DRV_TIM_DEVICE_ID_GPIOCNTR1 = 0x11ul,
  DRV_TIM_DEVICE_ID_GPIOCNTR2 = 0x12ul,
  DRV_TIM_DEVICE_ID_GPIOCNTR_MIN = DRV_TIM_DEVICE_ID_GPIOCNTR0,
  DRV_TIM_DEVICE_ID_GPIOCNTR_MAX = DRV_TIM_DEVICE_ID_GPIOCNTR2,
  DRV_TIM_DEVICE_ID_TIMER0 = 0x13ul,
  DRV_TIM_DEVICE_ID_TIMER1 = 0x14ul,
  DRV_TIM_DEVICE_ID_TIMER2 = 0x15ul,
  DRV_TIM_DEVICE_ID_TIMER_MIN = DRV_TIM_DEVICE_ID_TIMER0,
  DRV_TIM_DEVICE_ID_TIMER_MAX = DRV_TIM_DEVICE_ID_TIMER2,
  DRV_TIM_DEVICE_ID_SYSTIMECOMPARE = 0x16ul,
  DRV_TIM_DEVICE_ID_SYSTICK = 0x17ul,
  DRV_TIM_DEVICE_ID_SYSTIME_COM = 0x18ul,
  DRV_TIM_DEVICE_ID_SYSTIME_COM_UC = 0x19ul,
  DRV_TIM_DEVICE_ID_SYSTIME_APP = 0x1aul,
  DRV_TIM_DEVICE_ID_SYSTIME_MIN = DRV_TIM_DEVICE_ID_SYSTIME_COM,
  DRV_TIM_DEVICE_ID_SYSTIME_MAX = DRV_TIM_DEVICE_ID_SYSTIME_APP,
  DRV_TIM_DEVICE_ID_MIN = DRV_TIM_DEVICE_ID_GPIOCNTR0,
  DRV_TIM_DEVICE_ID_MAX = DRV_TIM_DEVICE_ID_SYSTIME_APP
}
 Enumeration of the available timer IDs. More...
 
enum  DRV_DMAC_DEVICE_ID_E {
  DRV_DMAC_DEVICE_ID_0 = 0x8u,
  DRV_DMAC_DEVICE_ID_1 = 0x9u,
  DRV_DMAC_DEVICE_ID_2 = 0xau,
  DRV_DMAC_DEVICE_ID_3 = 0xbu,
  DRV_DMAC_DEVICE_ID_MIN = DRV_DMAC_DEVICE_ID_0,
  DRV_DMAC_DEVICE_ID_MAX = DRV_DMAC_DEVICE_ID_3
}
 
enum  DRV_DMAC_PERIPHERAL_E {
  DRV_DMAC_PERIPHERAL_UART_SHARED_RX = 0u,
  DRV_DMAC_PERIPHERAL_UART_SHARED_TX = 1u,
  DRV_DMAC_PERIPHERAL_UART_APP_RX = 2u,
  DRV_DMAC_PERIPHERAL_UART_APP_TX = 3u,
  DRV_DMAC_PERIPHERAL_I2C_APP_MASTER = 4u,
  DRV_DMAC_PERIPHERAL_I2C_APP_SLAVE = 5u,
  DRV_DMAC_PERIPHERAL_SPI0_APP_RX = 6u,
  DRV_DMAC_PERIPHERAL_SPI0_APP_TX = 7u,
  DRV_DMAC_PERIPHERAL_SPI1_APP_RX = 8u,
  DRV_DMAC_PERIPHERAL_SPI1_APP_TX = 9u,
  DRV_DMAC_PERIPHERAL_SPI2_APP_RX = 10u,
  DRV_DMAC_PERIPHERAL_SPI2_APP_TX = 11u,
  DRV_DMAC_PERIPHERAL_SQI0_APP_RX = 12u,
  DRV_DMAC_PERIPHERAL_SQI0_APP_TX = 13u,
  DRV_DMAC_PERIPHERAL_SQI1_APP_RX = 14u,
  DRV_DMAC_PERIPHERAL_SQI1_APP_TX = 15u,
  DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX = 16u,
  DRV_DMAC_PERIPHERAL_UART_XPIC_APP_TX = 17u,
  DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_MASTER = 18u,
  DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_SLAVE = 19u,
  DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX = 20u,
  DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_TX = 21u,
  DRV_DMAC_PERIPHERAL_SQI_RX = 22u,
  DRV_DMAC_PERIPHERAL_SQI_TX = 23u,
  DRV_DMAC_PERIPHERAL_ETH_RX = 24u,
  DRV_DMAC_PERIPHERAL_ETH_TX = 25u,
  DRV_DMAC_PERIPHERAL_HASH = 26u,
  DRV_DMAC_PERIPHERAL_AES_IN = 27u,
  DRV_DMAC_PERIPHERAL_AES_OUT = 28u,
  DRV_DMAC_PERIPHERAL_NC = 29u,
  DRV_DMAC_PERIPHERAL_30_RESERVED = 30u,
  DRV_DMAC_PERIPHERAL_31_RESERVED = 31u,
  DRV_DMAC_PERIPHERAL_MEMORY = 32u
}
 
enum  DRV_UART_DEVICE_ID_E {
  DRV_UART_DEVICE_ID_UART0 = 0x07ul,
  DRV_UART_DEVICE_ID_UART1 = 0x08ul,
  DRV_UART_DEVICE_ID_UART2 = 0x09ul,
  DRV_UART_DEVICE_ID_MIN = DRV_UART_DEVICE_ID_UART0,
  DRV_UART_DEVICE_ID_MAX = DRV_UART_DEVICE_ID_UART2
}
 
enum  DRV_SPI_DEVICE_ID_E {
  DRV_SPI_DEVICE_ID_DEFAULT = 0x00ul,
  DRV_SPI_DEVICE_ID_SPI0 = 0x10ul,
  DRV_SPI_DEVICE_ID_SPI1 = 0x11ul,
  DRV_SPI_DEVICE_ID_SPI2 = 0x12ul,
  DRV_SPI_DEVICE_ID_SPI3 = 0x13ul,
  DRV_SPI_DEVICE_ID_SQI0 = 0x14ul,
  DRV_SPI_DEVICE_ID_SQI1 = 0x15ul,
  DRV_SPI_DEVICE_ID_SQI2 = 0x16ul,
  DRV_SPI_DEVICE_ID_MIN = DRV_SPI_DEVICE_ID_SPI0,
  DRV_SPI_DEVICE_ID_MAX = DRV_SPI_DEVICE_ID_SQI2,
  DRV_SPI_DEVICE_ID_SQI_BORDER = DRV_SPI_DEVICE_ID_SQI0,
  DRV_SPI_DEVICE_ID_QSPI_BORDER = DRV_SPI_DEVICE_ID_MAX+1
}
 The SPI device IDs. More...
 
enum  DRV_I2C_DEVICE_ID_E {
  DRV_I2C_DEVICE_ID_I2C0 = 0x1ul,
  DRV_I2C_DEVICE_ID_I2C1 = 0x02ul,
  DRV_I2C_DEVICE_ID_MIN = DRV_I2C_DEVICE_ID_I2C0,
  DRV_I2C_DEVICE_ID_MAX = DRV_I2C_DEVICE_ID_I2C1
}
 
enum  DRV_ADC_SEQ_DEVICE_ID_E {
  DRV_ADC_SEQ_DEVICE_ID_ADC0 = 0x10u,
  DRV_ADC_SEQ_DEVICE_ID_ADC1 = 0x11u,
  DRV_ADC_SEQ_DEVICE_ID_ADC2 = 0x12u,
  DRV_ADC_SEQ_DEVICE_ID_ADC3 = 0x13u,
  DRV_ADC_SEQ_DEVICE_ID_MIN = DRV_ADC_SEQ_DEVICE_ID_ADC0,
  DRV_ADC_SEQ_DEVICE_ID_MAX = DRV_ADC_SEQ_DEVICE_ID_ADC3
}
 

Detailed Description

Macro Definition Documentation

#define ADC_APP_DEVICE   ((DRV_ADC_DEVICE_T*) madc_BASE)

Definition at line 555 of file netx_drv_csp_netx90_app.h.

#define ADC_SEQ0_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq0_BASE)

Definition at line 556 of file netx_drv_csp_netx90_app.h.

#define ADC_SEQ1_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq1_BASE)

Definition at line 557 of file netx_drv_csp_netx90_app.h.

#define ADC_SEQ2_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq2_BASE)

Definition at line 558 of file netx_drv_csp_netx90_app.h.

#define ADC_SEQ3_APP_DEVICE   ((DRV_ADC_SEQ_DEVICE_T*) madc_seq3_BASE)

Definition at line 559 of file netx_drv_csp_netx90_app.h.

#define DMAC_APP_CH0_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE)

Definition at line 393 of file netx_drv_csp_netx90_app.h.

#define DMAC_APP_CH1_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+1)

Definition at line 394 of file netx_drv_csp_netx90_app.h.

#define DMAC_APP_CH2_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+2)

Definition at line 395 of file netx_drv_csp_netx90_app.h.

#define DMAC_APP_CH3_DEVICE   ((DRV_DMAC_CH_DEVICE_T*) dmac_app_ch_BASE+3)

Definition at line 396 of file netx_drv_csp_netx90_app.h.

#define DMAC_APP_REG_DEVICE   ((DRV_DMAC_REG_DEVICE_T*) dmac_app_reg_BASE)

Definition at line 401 of file netx_drv_csp_netx90_app.h.

#define DMAC_MUX_APP_DEVICE   ((DRV_DMAC_MUX_DEVICE_T*) dmac_mux_app_BASE)

Definition at line 403 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_COUNT   4

Definition at line 568 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_DEVICE_COUNT   1

Definition at line 561 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_DEVICE_LIST   { ADC_APP_DEVICE }

Definition at line 562 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_INPUT_COUNT01   4

Definition at line 571 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_INPUT_COUNT23   8

Definition at line 572 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_INPUTS_MAX   8

Definition at line 569 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_MEASUREMENTS_MAX   8

Definition at line 570 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_MODULE_SUPPORTED

Definition at line 574 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_SEQ_DEVICE_COUNT   4

Definition at line 564 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_SEQ_DEVICE_IRQ_LIST   { madc_seq0_IRQn, madc_seq1_IRQn, madc_seq2_IRQn, madc_seq3_IRQn }

Definition at line 566 of file netx_drv_csp_netx90_app.h.

#define DRV_ADC_SEQ_DEVICE_LIST   { ADC_SEQ0_APP_DEVICE, ADC_SEQ1_APP_DEVICE, ADC_SEQ2_APP_DEVICE, ADC_SEQ3_APP_DEVICE }

Definition at line 565 of file netx_drv_csp_netx90_app.h.

#define DRV_ASIC_CTRL_DEVICE   ((DRV_ASIC_CTRL_T*) asic_ctrl_BASE)

Definition at line 53 of file netx_drv_csp_netx90_app.h.

#define DRV_BISS_MODULE_SUPPORTED

Definition at line 47 of file netx_drv_csp_netx90_app.h.

#define DRV_BOD_IRQ   bod_IRQn

Definition at line 117 of file netx_drv_csp_netx90_app.h.

#define DRV_BOD_IRQ_COUNT   1

Definition at line 118 of file netx_drv_csp_netx90_app.h.

#define DRV_CANCTRL_MODULE_SUPPORTED

Definition at line 48 of file netx_drv_csp_netx90_app.h.

#define DRV_CORTEX_MODULE_SUPPORTED

Definition at line 46 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_BOD   0x500070u

Brown out ID.

Definition at line 331 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_0   0x100000u

GPIO channel 0 ID.

Definition at line 232 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_1   0x100001u

GPIO channel 1 ID.

Definition at line 233 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_2   0x100002u

GPIO channel 2 ID.

Definition at line 234 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_3   0x100003u

GPIO channel 3 ID.

Definition at line 235 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_4   0x100004u

GPIO channel 4 ID.

Definition at line 236 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_5   0x100005u

GPIO channel 5 ID.

Definition at line 237 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_6   0x100006u

GPIO channel 6 ID.

Definition at line 238 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_7   0x100007u

GPIO channel 7 ID.

Definition at line 239 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_MAX   DRV_DIO_ID_GPIO_7

The highest GPIO channel id.

Definition at line 240 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_GPIO_MIN   DRV_DIO_ID_GPIO_0

The available io channels by id.The lowest GPIO channel id.

Definition at line 231 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A0   0x400020u

HIF channel A0

Definition at line 303 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A1   0x400021u

HIF channel A1

Definition at line 304 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A10   0x40002au

HIF channel A10

Definition at line 313 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A11   0x40002bu

HIF channel A11

Definition at line 314 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A12   0x40002cu

HIF channel A12

Definition at line 315 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A13   0x40002du

HIF channel A13

Definition at line 316 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A14   0x40002eu

HIF channel A14

Definition at line 317 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A15   0x40002fu

HIF channel A15

Definition at line 318 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A16   0x400030u

HIF channel A16

Definition at line 319 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A17   0x400031u

HIF channel A17

Definition at line 320 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A2   0x400022u

HIF channel A2

Definition at line 305 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A3   0x400023u

HIF channel A3

Definition at line 306 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A4   0x400024u

HIF channel A4

Definition at line 307 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A5   0x400025u

HIF channel A5

Definition at line 308 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A6   0x400026u

HIF channel A6

Definition at line 309 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A7   0x400027u

HIF channel A7

Definition at line 310 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A8   0x400028u

HIF channel A8

Definition at line 311 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_A9   0x400029u

HIF channel A9

Definition at line 312 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_BHEN   0x400039u

HIF channel BHEN

Definition at line 322 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_CSN   0x40003cu

HIF channel CSN

Definition at line 325 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D0   0x400000u

HIF channel D0

Definition at line 286 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D1   0x400001u

HIF channel D1

Definition at line 287 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D10   0x40000au

HIF channel D10

Definition at line 296 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D11   0x40000bu

HIF channel D11

Definition at line 297 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D12   0x40000cu

HIF channel D12

Definition at line 298 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D13   0x40000du

HIF channel D13

Definition at line 299 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D14   0x40000eu

HIF channel D14

Definition at line 300 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D15   0x40000fu

HIF channel D15

Definition at line 301 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D2   0x400002u

HIF channel D2

Definition at line 288 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D3   0x400003u

HIF channel D3

Definition at line 289 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D4   0x400004u

HIF channel D4

Definition at line 290 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D5   0x400005u

HIF channel D5

Definition at line 291 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D6   0x400006u

HIF channel D6

Definition at line 292 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D7   0x400007u

HIF channel D7

Definition at line 293 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D8   0x400008u

HIF channel D8

Definition at line 294 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_D9   0x400009u

HIF channel D9

Definition at line 295 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_DIRQ   0x40003eu

HIF channel DIRQ

Definition at line 327 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_MAX   DRV_DIO_ID_HIF_SDCLK

The highest HIF channel id.

Definition at line 329 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_MIN   DRV_DIO_ID_HIF_D0

The lowest HIF channel id.

Definition at line 285 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_RDN   0x40003au

HIF channel RDN

Definition at line 323 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_RDY   0x40003du

HIF channel RDY

Definition at line 326 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_RESERVED0

Definition at line 302 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_RESERVED1

Definition at line 321 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_SDCLK   0x40003fu

HIF channel SDCLK

Definition at line 328 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_HIF_WRN   0x40003bu

HIF channel WRN

Definition at line 324 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_0   0x300000u

MMIO channel 0 ID.

Definition at line 275 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_1   0x300001u

MMIO channel 1 ID.

Definition at line 276 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_2   0x300002u

MMIO channel 2 ID.

Definition at line 277 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_3   0x300003u

MMIO channel 3 ID.

Definition at line 278 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_4   0x300004u

MMIO channel 4 ID.

Definition at line 279 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_5   0x300005u

MMIO channel 5 ID.

Definition at line 280 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_6   0x300006u

MMIO channel 6 ID.

Definition at line 281 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_7   0x300007u

MMIO channel 7 ID.

Definition at line 282 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_MAX   DRV_DIO_ID_MMIO_7

The highest MMIO channel id.

Definition at line 283 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_MMIO_MIN   DRV_DIO_ID_MMIO_0

The lowest MMIO channel id.

Definition at line 274 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_0   0x200000u

PIO channel 0 ID.

Definition at line 243 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_1   0x200001u

PIO channel 1 ID.

Definition at line 244 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_10   0x20000au

PIO channel 10 ID.

Definition at line 253 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_11   0x20000bu

PIO channel 11 ID.

Definition at line 254 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_12   0x20000cu

PIO channel 12 ID.

Definition at line 255 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_13   0x20000du

PIO channel 13 ID.

Definition at line 256 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_14   0x20000eu

PIO channel 14 ID.

Definition at line 257 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_15   0x20000fu

PIO channel 15 ID.

Definition at line 258 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_16   0x200010u

PIO channel 16 ID.

Definition at line 259 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_17   0x200011u

PIO channel 17 ID.

Definition at line 260 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_18   0x200012u

PIO channel 18 ID.

Definition at line 261 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_19   0x200013u

PIO channel 19 ID.

Definition at line 262 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_2   0x200002u

PIO channel 2 ID.

Definition at line 245 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_20   0x200014u

PIO channel 20 ID.

Definition at line 263 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_21   0x200015u

PIO channel 21 ID.

Definition at line 264 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_22   0x200016u

PIO channel 22 ID.

Definition at line 265 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_23   0x200017u

PIO channel 23 ID.

Definition at line 266 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_24   0x200018u

PIO channel 24 ID.

Definition at line 267 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_25   0x200019u

PIO channel 25 ID.

Definition at line 268 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_26   0x20001au

PIO channel 26 ID.

Definition at line 269 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_27   0x20001bu

PIO channel 27 ID.

Definition at line 270 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_28   0x20001cu

PIO channel 28 ID.

Definition at line 271 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_3   0x200003u

PIO channel 3 ID.

Definition at line 246 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_4   0x200004u

PIO channel 4 ID.

Definition at line 247 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_5   0x200005u

PIO channel 5 ID.

Definition at line 248 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_6   0x200006u

PIO channel 6 ID.

Definition at line 249 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_7   0x200007u

PIO channel 7 ID.

Definition at line 250 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_8   0x200008u

PIO channel 8 ID.

Definition at line 251 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_9   0x200009u

PIO channel 9 ID.

Definition at line 252 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_MAX   DRV_DIO_ID_PIO_28

The highest PIO channel id.

Definition at line 272 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_ID_PIO_MIN   DRV_DIO_ID_PIO_0

The lowest PIO channel id.

Definition at line 242 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_IRQ_COUNT   DRV_GPIO_IRQ_COUNT + DRV_HIF_IRQ_COUNT + DRV_BOD_IRQ_COUNT + DRV_PIO_IRQ_COUNT

Definition at line 119 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_LINE_MSK_GPIO   (uint64_t)0x00000000000000FFull

GPIO line select.

Definition at line 127 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_LINE_MSK_HIF   (uint64_t)0xFE03FFFF0000FFFFull

HIF line select.

Definition at line 130 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_LINE_MSK_MMIO   (uint64_t)0x00000000000000FFull

MMIO line selected.

Definition at line 129 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_LINE_MSK_NONE   (uint64_t)0x0000000000000000ull

The available output lines.

Each device has its own line registers.No line selected.

Definition at line 126 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_LINE_MSK_PIO   (uint64_t)0x000000001FFFFFFFull

PIO line select.

Definition at line 128 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MODULE_SUPPORTED

Definition at line 98 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_0   (uint64_t)0x0000000000000001ull

The available IO channels by bit position usable as mask.GPIO 0

Definition at line 135 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_1   (uint64_t)0x0000000000000002ull

GPIO 1

Definition at line 136 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_2   (uint64_t)0x0000000000000004ull

GPIO 2

Definition at line 137 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_3   (uint64_t)0x0000000000000008ull

GPIO 3

Definition at line 138 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_4   (uint64_t)0x0000000000000010ull

GPIO 4

Definition at line 139 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_5   (uint64_t)0x0000000000000020ull

GPIO 5

Definition at line 140 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_6   (uint64_t)0x0000000000000040ull

GPIO 6

Definition at line 141 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_GPIO_7   (uint64_t)0x0000000000000080ull

GPIO 7

Definition at line 142 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A0   (uint64_t)0x0000000100000000ull

HIF A0

Definition at line 201 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A1   (uint64_t)0x0000000200000000ull

HIF A1

Definition at line 202 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A10   (uint64_t)0x0000040000000000ull

HIF A10

Definition at line 211 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A11   (uint64_t)0x0000080000000000ull

HIF A11

Definition at line 212 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A12   (uint64_t)0x0000100000000000ull

HIF A12

Definition at line 213 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A13   (uint64_t)0x0000200000000000ull

HIF A13

Definition at line 214 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A14   (uint64_t)0x0000400000000000ull

HIF A14

Definition at line 215 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A15   (uint64_t)0x0000800000000000ull

HIF A15

Definition at line 216 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A16   (uint64_t)0x0001000000000000ull

HIF A16

Definition at line 217 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A17   (uint64_t)0x0002000000000000ull

HIF A17

Definition at line 218 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A2   (uint64_t)0x0000000400000000ull

HIF A2

Definition at line 203 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A3   (uint64_t)0x0000000800000000ull

HIF A3

Definition at line 204 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A4   (uint64_t)0x0000001000000000ull

HIF A4

Definition at line 205 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A5   (uint64_t)0x0000002000000000ull

HIF A5

Definition at line 206 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A6   (uint64_t)0x0000004000000000ull

HIF A6

Definition at line 207 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A7   (uint64_t)0x0000008000000000ull

HIF A7

Definition at line 208 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A8   (uint64_t)0x0000010000000000ull

HIF A8

Definition at line 209 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A9   (uint64_t)0x0000020000000000ull

HIF A9

Definition at line 210 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_A_RESERVED   (uint64_t)0x01fc000000000000ull

RESERVED

Definition at line 219 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_BHEN   (uint64_t)0x0200000000000000ull

HIF BHEN

Definition at line 220 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_CSN   (uint64_t)0x1000000000000000ull

HIF CSN

Definition at line 223 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D0   (uint64_t)0x0000000000000001ull

HIF D0

Definition at line 183 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D1   (uint64_t)0x0000000000000002ull

HIF D1

Definition at line 184 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D10   (uint64_t)0x0000000000000400ull

HIF D10

Definition at line 193 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D11   (uint64_t)0x0000000000000800ull

HIF D11

Definition at line 194 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D12   (uint64_t)0x0000000000001000ull

HIF D12

Definition at line 195 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D13   (uint64_t)0x0000000000002000ull

HIF D13

Definition at line 196 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D14   (uint64_t)0x0000000000004000ull

HIF D14

Definition at line 197 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D15   (uint64_t)0x0000000000008000ull

HIF D15

Definition at line 198 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D2   (uint64_t)0x0000000000000004ull

HIF D2

Definition at line 185 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D3   (uint64_t)0x0000000000000008ull

HIF D3

Definition at line 186 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D4   (uint64_t)0x0000000000000010ull

HIF D4

Definition at line 187 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D5   (uint64_t)0x0000000000000020ull

HIF D5

Definition at line 188 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D6   (uint64_t)0x0000000000000040ull

HIF D6

Definition at line 189 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D7   (uint64_t)0x0000000000000080ull

HIF D7

Definition at line 190 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D8   (uint64_t)0x0000000000000100ull

HIF D8

Definition at line 191 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D9   (uint64_t)0x0000000000000200ull

HIF D9

Definition at line 192 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_D_RESERVED   (uint64_t)0x00000000FFFF0000ull

RESERVED

Definition at line 199 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_DIRQ   (uint64_t)0x4000000000000000ull

HIF DIRQ

Definition at line 225 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_RDN   (uint64_t)0x0400000000000000ull

HIF RDN

Definition at line 221 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_RDY   (uint64_t)0x2000000000000000ull

HIF RDY

Definition at line 224 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_SDCLK   (uint64_t)0x8000000000000000ull

HIF SDCLK

Definition at line 226 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_HIF_WRN   (uint64_t)0x0800000000000000ull

HIF WRN

Definition at line 222 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_0   (uint64_t)0x0000000000000001ull

MMIO 0

Definition at line 174 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_1   (uint64_t)0x0000000000000002ull

MMIO 1

Definition at line 175 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_2   (uint64_t)0x0000000000000004ull

MMIO 2

Definition at line 176 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_3   (uint64_t)0x0000000000000008ull

MMIO 3

Definition at line 177 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_4   (uint64_t)0x0000000000000010ull

MMIO 4

Definition at line 178 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_5   (uint64_t)0x0000000000000020ull

MMIO 5

Definition at line 179 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_6   (uint64_t)0x0000000000000040ull

MMIO 6

Definition at line 180 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_MMIO_7   (uint64_t)0x0000000000000080ull

MMIO 7

Definition at line 181 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_0   (uint64_t)0x0000000000000001ull

PIO 0

Definition at line 144 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_1   (uint64_t)0x0000000000000002ull

PIO 1

Definition at line 145 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_10   (uint64_t)0x0000000000000400ull

PIO 10

Definition at line 154 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_11   (uint64_t)0x0000000000000800ull

PIO 11

Definition at line 155 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_12   (uint64_t)0x0000000000001000ull

PIO 12

Definition at line 156 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_13   (uint64_t)0x0000000000002000ull

PIO 13

Definition at line 157 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_14   (uint64_t)0x0000000000004000ull

PIO 14

Definition at line 158 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_15   (uint64_t)0x0000000000008000ull

PIO 15

Definition at line 159 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_16   (uint64_t)0x0000000000010000ull

PIO 16

Definition at line 160 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_17   (uint64_t)0x0000000000020000ull

PIO 17

Definition at line 161 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_18   (uint64_t)0x0000000000040000ull

PIO 18

Definition at line 162 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_19   (uint64_t)0x0000000000080000ull

PIO 19

Definition at line 163 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_2   (uint64_t)0x0000000000000004ull

PIO 2

Definition at line 146 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_20   (uint64_t)0x0000000000100000ull

PIO 20

Definition at line 164 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_21   (uint64_t)0x0000000000200000ull

PIO 21

Definition at line 165 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_22   (uint64_t)0x0000000000400000ull

PIO 22

Definition at line 166 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_23   (uint64_t)0x0000000000800000ull

PIO 23

Definition at line 167 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_24   (uint64_t)0x0000000001000000ull

PIO 24

Definition at line 168 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_25   (uint64_t)0x0000000002000000ull

PIO 25

Definition at line 169 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_26   (uint64_t)0x0000000004000000ull

PIO 26

Definition at line 170 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_27   (uint64_t)0x0000000008000000ull

PIO 27

Definition at line 171 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_28   (uint64_t)0x0000000010000000ull

PIO 28

Definition at line 172 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_3   (uint64_t)0x0000000000000008ull

PIO 3

Definition at line 147 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_4   (uint64_t)0x0000000000000010ull

PIO 4

Definition at line 148 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_5   (uint64_t)0x0000000000000020ull

PIO 5

Definition at line 149 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_6   (uint64_t)0x0000000000000040ull

PIO 6

Definition at line 150 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_7   (uint64_t)0x0000000000000080ull

PIO 7

Definition at line 151 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_8   (uint64_t)0x0000000000000100ull

PIO 8

Definition at line 152 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_MSK_PIO_9   (uint64_t)0x0000000000000200ull

PIO 9

Definition at line 153 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_PIO_INVERT_SUPPORTED

Definition at line 108 of file netx_drv_csp_netx90_app.h.

#define DRV_DIO_PIO_IRQ_SUPPORTED

Definition at line 109 of file netx_drv_csp_netx90_app.h.

#define DRV_DMAC_CH_DEVICE_COUNT   4

Definition at line 397 of file netx_drv_csp_netx90_app.h.

#define DRV_DMAC_CH_DEVICE_LIST   { DMAC_APP_CH0_DEVICE, DMAC_APP_CH1_DEVICE, DMAC_APP_CH2_DEVICE, DMAC_APP_CH3_DEVICE }

Definition at line 399 of file netx_drv_csp_netx90_app.h.

#define DRV_DMAC_MODULE_SUPPORTED

Definition at line 378 of file netx_drv_csp_netx90_app.h.

#define DRV_DMAC_REG_IRQ   dmac_app_IRQn

Definition at line 398 of file netx_drv_csp_netx90_app.h.

#define DRV_ETH_XPIC_MODULE_SUPPORTED

Definition at line 50 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO0_IRQ   gpio_app0_IRQn

Definition at line 112 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO_COUNTER_IRQs   gpio_app_timer0_IRQn, gpio_app_timer1_IRQn, gpio_app_timer2_IRQn

Definition at line 371 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO_DEVICE   ((DRV_GPIO_DEVICE_T*) gpio_app_BASE)

Definition at line 105 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO_IRQ_COUNT   8

Definition at line 110 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO_IRQ_LIST   gpio_app0_IRQn, gpio_app1_IRQn, gpio_app2_IRQn, gpio_app3_IRQn, gpio_app4_IRQn, gpio_app5_IRQn, gpio_app6_IRQn, gpio_app7_IRQn

Definition at line 111 of file netx_drv_csp_netx90_app.h.

#define DRV_GPIO_XPIC_DEVICE   ((DRV_GPIO_DEVICE_T*) gpio_xpic_app_BASE)

Definition at line 106 of file netx_drv_csp_netx90_app.h.

#define DRV_HIF_IO_DEVICE   ((DRV_HIF_IO_DEVICE_T*) hif_io_ctrl_BASE)

Definition at line 104 of file netx_drv_csp_netx90_app.h.

#define DRV_HIF_IRQ_COUNT   4

Definition at line 113 of file netx_drv_csp_netx90_app.h.

#define DRV_HIFPIO_IRQ   hif_pio_arm_IRQn

Definition at line 114 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_DEVICE_COUNT   2

Definition at line 534 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_DEVICE_IRQ_LIST   { i2c_app_IRQn, i2c_xpic_app_IRQn }

Definition at line 536 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_DEVICE_LIST   { I2C_DEVICE_APP0, I2C_DEVICE_APP1 }

Definition at line 535 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_IRQ_HANDLER0   I2C_IRQHandler

Definition at line 531 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_IRQ_HANDLER1   I2CXPIC_IRQHandler

Definition at line 533 of file netx_drv_csp_netx90_app.h.

#define DRV_I2C_MODULE_SUPPORTED

Definition at line 516 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_DEVICE   ((DRV_MLED_DEVICE_T*) mled_ctrl_app_BASE)

Definition at line 57 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_DEVICE_COUNT   1

Definition at line 58 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_DEVICE_LIST   { DRV_MLED_DEVICE }

Definition at line 59 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_0   0x000000u

MLED channel 0 ID.

Definition at line 80 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_1   0x000001u

MLED channel 1 ID.

Definition at line 81 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_10   0x00000au

MLED channel 10 ID.

Definition at line 90 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_11   0x00000bu

MLED channel 11 ID.

Definition at line 91 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_12   0x00000cu

MLED channel 12 ID.

Definition at line 92 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_13   0x00000du

MLED channel 13 ID.

Definition at line 93 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_14   0x00000eu

MLED channel 14 ID.

Definition at line 94 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_15   0x00000fu

MLED channel 15 ID.

Definition at line 95 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_2   0x000002u

MLED channel 2 ID.

Definition at line 82 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_3   0x000003u

MLED channel 3 ID.

Definition at line 83 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_4   0x000004u

MLED channel 4 ID.

Definition at line 84 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_5   0x000005u

MLED channel 5 ID.

Definition at line 85 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_6   0x000006u

MLED channel 6 ID.

Definition at line 86 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_7   0x000007u

MLED channel 7 ID.

Definition at line 87 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_8   0x000008u

MLED channel 8 ID.

Definition at line 88 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_9   0x000009u

MLED channel 9 ID.

Definition at line 89 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_MAX   DRV_MLED_ID_15

The highest MMIO channel id.

Definition at line 96 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_ID_MIN   DRV_MLED_ID_0

The lowest MMIO channel id.

Definition at line 79 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_LINE_MSK   (uint32_t)0x0000FFFFull

MMIO line selected.

Definition at line 77 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MODULE_SUPPORTED

Definition at line 55 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_0   (uint32_t)0x00000001ull

MLED 0

Definition at line 61 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_1   (uint32_t)0x00000002ull

MLED 1

Definition at line 62 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_10   (uint32_t)0x00000400ull

MLED 10

Definition at line 71 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_11   (uint32_t)0x00000800ull

MLED 11

Definition at line 72 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_12   (uint32_t)0x00001000ull

MLED 12

Definition at line 73 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_13   (uint32_t)0x00002000ull

MLED 13

Definition at line 74 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_14   (uint32_t)0x00004000ull

MLED 14

Definition at line 75 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_15   (uint32_t)0x00008000ull

MLED 15

Definition at line 76 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_2   (uint32_t)0x00000004ull

MLED 2

Definition at line 63 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_3   (uint32_t)0x00000008ull

MLED 3

Definition at line 64 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_4   (uint32_t)0x00000010ull

MLED 4

Definition at line 65 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_5   (uint32_t)0x00000020ull

MLED 5

Definition at line 66 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_6   (uint32_t)0x00000040ull

MLED 6

Definition at line 67 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_7   (uint32_t)0x00000080ull

MLED 7

Definition at line 68 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_8   (uint32_t)0x00000100ull

MLED 8

Definition at line 69 of file netx_drv_csp_netx90_app.h.

#define DRV_MLED_MSK_9   (uint32_t)0x00000200ull

MLED 9

Definition at line 70 of file netx_drv_csp_netx90_app.h.

#define DRV_MMIO_DEVICE   ((DRV_MMIO_DEVICE_T*) mmio_ctrl_BASE)

Definition at line 103 of file netx_drv_csp_netx90_app.h.

#define DRV_PIO_DEVICE   ((DRV_PIO_DEVICE_T*) pio_app_BASE)

Definition at line 107 of file netx_drv_csp_netx90_app.h.

#define DRV_PIO_IRQ   pio0_app_IRQn

Definition at line 116 of file netx_drv_csp_netx90_app.h.

#define DRV_PIO_IRQ_COUNT   29

Definition at line 115 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_DEVICE_COUNT   7

Definition at line 511 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_DEVICE_DMA_LIST   { DRV_DMAC_PERIPHERAL_SPI0_APP_RX, DRV_DMAC_PERIPHERAL_SPI1_APP_RX, DRV_DMAC_PERIPHERAL_SPI2_APP_RX, DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_SQI_RX, DRV_DMAC_PERIPHERAL_SQI0_APP_RX, DRV_DMAC_PERIPHERAL_SQI1_APP_RX }

Definition at line 514 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_DEVICE_IRQ_LIST   { spi0_app_IRQn, spi1_app_IRQn, spi2_app_IRQn, spi_xpic_app_IRQn, sqi_IRQn, sqi0_app_IRQn, sqi1_app_IRQn }

Definition at line 513 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_DEVICE_LIST   { {(uintptr_t) SPI_DEVICE_APP0}, {(uintptr_t) SPI_DEVICE_APP1}, {(uintptr_t) SPI_DEVICE_APP2}, {(uintptr_t) SPI_DEVICE_APP3}, {(uintptr_t) SQI_DEVICE_SHARED}, {(uintptr_t) SQI_DEVICE_APP0}, {(uintptr_t) SQI_DEVICE_APP1}}

Definition at line 512 of file netx_drv_csp_netx90_app.h.

#define DRV_SPI_MODULE_SUPPORTED

Definition at line 467 of file netx_drv_csp_netx90_app.h.

#define DRV_SYSTICK_IRQ   SysTick_IRQn

Definition at line 374 of file netx_drv_csp_netx90_app.h.

#define DRV_SYSTIME_COMPARE_IRQ   timer_app_systime_s_IRQn

Definition at line 373 of file netx_drv_csp_netx90_app.h.

#define DRV_SYSTIME_DEVICE   ((systime_app_Type*) systime_app_BASE)

Definition at line 370 of file netx_drv_csp_netx90_app.h.

#define DRV_SYSTIME_LT_DEVICE   ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_app_BASE)

Definition at line 367 of file netx_drv_csp_netx90_app.h.

#define DRV_SYSTIME_LT_XPIC_DEVICE   ((DRV_SYSTIME_LT_DEVICE_T*) systime_lt_xpic_app_BASE)

Definition at line 368 of file netx_drv_csp_netx90_app.h.

#define DRV_TIM_IRQ_COUNT   8u

Definition at line 375 of file netx_drv_csp_netx90_app.h.

#define DRV_TIM_IRQ_LIST   { DRV_GPIO_COUNTER_IRQs, DRV_TIMER_IRQs, DRV_SYSTIME_COMPARE_IRQ, DRV_SYSTICK_IRQ }

Definition at line 376 of file netx_drv_csp_netx90_app.h.

#define DRV_TIM_MODULE_SUPPORTED

Definition at line 333 of file netx_drv_csp_netx90_app.h.

#define DRV_TIMER_DEVICE   ((DRV_TIMER_DEVICE_T*) timer_app_BASE)

Definition at line 364 of file netx_drv_csp_netx90_app.h.

#define DRV_TIMER_IRQs   timer_app0_IRQn, timer_app1_IRQn, timer_app2_IRQn

Definition at line 372 of file netx_drv_csp_netx90_app.h.

#define DRV_TIMER_XPIC_DEVICE   ((DRV_TIMER_DEVICE_T*) timer_xpic_app_BASE)

Definition at line 365 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_DEVICE_COUNT   3

Definition at line 462 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_DEVICE_DMA_LIST   { DRV_DMAC_PERIPHERAL_UART_APP_RX, DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX, DRV_DMAC_PERIPHERAL_UART_SHARED_RX }

Definition at line 465 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_DEVICE_IRQ_LIST   { uart_app_IRQn, uart_xpic_app_IRQn, uart_IRQn }

Definition at line 464 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_DEVICE_LIST   { UART_DEVICE_APP, UART_DEVICE_XPIC_APP, UART_DEVICE_SHARED }

Definition at line 463 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_IRQ_HANDLER0   UARTAPP_IRQHandler

Definition at line 457 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_IRQ_HANDLER1   UARTXPIC_IRQHandler

Definition at line 459 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_IRQ_HANDLER2   UART_IRQHandler

Definition at line 461 of file netx_drv_csp_netx90_app.h.

#define DRV_UART_MODULE_SUPPORTED

Definition at line 441 of file netx_drv_csp_netx90_app.h.

#define DRV_XPIC_MODULE_SUPPORTED

Definition at line 49 of file netx_drv_csp_netx90_app.h.

#define I2C_DEVICE_APP0   ((DRV_I2C_DEVICE_T*) i2c_app_BASE)

Definition at line 530 of file netx_drv_csp_netx90_app.h.

#define I2C_DEVICE_APP1   ((DRV_I2C_DEVICE_T*) i2c_xpic_app_BASE)

Definition at line 532 of file netx_drv_csp_netx90_app.h.

#define SPI_DEVICE_APP0   ((DRV_SPI_DEVICE_T*) spi0_app_BASE)

Definition at line 504 of file netx_drv_csp_netx90_app.h.

#define SPI_DEVICE_APP1   ((DRV_SPI_DEVICE_T*) spi1_app_BASE)

Definition at line 505 of file netx_drv_csp_netx90_app.h.

#define SPI_DEVICE_APP2   ((DRV_SPI_DEVICE_T*) spi2_app_BASE)

Definition at line 506 of file netx_drv_csp_netx90_app.h.

#define SPI_DEVICE_APP3   ((DRV_SPI_DEVICE_T*) spi_xpic_app_BASE)

Definition at line 507 of file netx_drv_csp_netx90_app.h.

#define SQI_DEVICE_APP0   ((DRV_SQI_DEVICE_T*) sqi0_app_BASE)

Definition at line 509 of file netx_drv_csp_netx90_app.h.

#define SQI_DEVICE_APP1   ((DRV_SQI_DEVICE_T*) sqi1_app_BASE)

Definition at line 510 of file netx_drv_csp_netx90_app.h.

#define SQI_DEVICE_SHARED   ((DRV_SQI_DEVICE_T*) sqi_BASE)

Definition at line 508 of file netx_drv_csp_netx90_app.h.

#define UART_DEVICE_APP   ((DRV_UART_DEVICE_T*) uart_app_BASE)

Definition at line 458 of file netx_drv_csp_netx90_app.h.

#define UART_DEVICE_SHARED   ((DRV_UART_DEVICE_T*) uart_BASE)

Definition at line 456 of file netx_drv_csp_netx90_app.h.

#define UART_DEVICE_XPIC_APP   ((DRV_UART_DEVICE_T*) uart_xpic_app_BASE)

Definition at line 460 of file netx_drv_csp_netx90_app.h.

Typedef Documentation

typedef madc_Type DRV_ADC_DEVICE_T

Definition at line 552 of file netx_drv_csp_netx90_app.h.

typedef madc_seq0_Type DRV_ADC_SEQ_DEVICE_T

Definition at line 553 of file netx_drv_csp_netx90_app.h.

typedef asic_ctrl_Type DRV_ASIC_CTRL_T

Definition at line 52 of file netx_drv_csp_netx90_app.h.

typedef dmac_app_ch_Type DRV_DMAC_CH_DEVICE_T

Definition at line 392 of file netx_drv_csp_netx90_app.h.

typedef dmac_mux_app_Type DRV_DMAC_MUX_DEVICE_T

Definition at line 402 of file netx_drv_csp_netx90_app.h.

typedef dmac_app_reg_Type DRV_DMAC_REG_DEVICE_T

Definition at line 400 of file netx_drv_csp_netx90_app.h.

typedef gpio_app_Type DRV_GPIO_DEVICE_T

Definition at line 101 of file netx_drv_csp_netx90_app.h.

typedef hif_io_ctrl_Type DRV_HIF_IO_DEVICE_T

Definition at line 100 of file netx_drv_csp_netx90_app.h.

typedef i2c_app_Type DRV_I2C_DEVICE_T

Definition at line 529 of file netx_drv_csp_netx90_app.h.

typedef mled_ctrl_app_Type DRV_MLED_DEVICE_T

Definition at line 56 of file netx_drv_csp_netx90_app.h.

typedef mmio_ctrl_Type DRV_MMIO_DEVICE_T

Definition at line 99 of file netx_drv_csp_netx90_app.h.

typedef pio_app_Type DRV_PIO_DEVICE_T

Definition at line 102 of file netx_drv_csp_netx90_app.h.

typedef spi0_app_Type DRV_SPI_DEVICE_T

Definition at line 496 of file netx_drv_csp_netx90_app.h.

typedef sqi_Type DRV_SQI_DEVICE_T

Definition at line 497 of file netx_drv_csp_netx90_app.h.

typedef systime_app_Type DRV_SYSTIME_DEVICE_T

Definition at line 369 of file netx_drv_csp_netx90_app.h.

typedef systime_lt_app_Type DRV_SYSTIME_LT_DEVICE_T

Definition at line 366 of file netx_drv_csp_netx90_app.h.

typedef timer_app_Type DRV_TIMER_DEVICE_T

Definition at line 363 of file netx_drv_csp_netx90_app.h.

typedef uart_app_Type DRV_UART_DEVICE_T

Definition at line 455 of file netx_drv_csp_netx90_app.h.

Enumeration Type Documentation

enum DRV_ADC_SEQ_DEVICE_ID_E

The adc device IDs.

They are used to identify the adc devices in the driver context.

Enumerator
DRV_ADC_SEQ_DEVICE_ID_ADC0 

The ADC drivers internal id for ADC0.

DRV_ADC_SEQ_DEVICE_ID_ADC1 

The ADC drivers internal id for ADC1.

DRV_ADC_SEQ_DEVICE_ID_ADC2 

The ADC drivers internal id for ADC2.

DRV_ADC_SEQ_DEVICE_ID_ADC3 

The ADC drivers internal id for ADC3.

DRV_ADC_SEQ_DEVICE_ID_MIN 

Min value for boundary checks.

DRV_ADC_SEQ_DEVICE_ID_MAX 

Max value for boundary checks.

Definition at line 543 of file netx_drv_csp_netx90_app.h.

enum DRV_DMAC_DEVICE_ID_E

Enumeration of the available dmac channels.

Enumerator
DRV_DMAC_DEVICE_ID_0 

The DMAC drivers id for channel 0.

DRV_DMAC_DEVICE_ID_1 

The DMAC drivers id for channel 1.

DRV_DMAC_DEVICE_ID_2 

The DMAC drivers id for channel 2.

DRV_DMAC_DEVICE_ID_3 

The DMAC drivers id for channel 3.

DRV_DMAC_DEVICE_ID_MIN 

The ADC Sequencer drivers first device ID.

DRV_DMAC_DEVICE_ID_MAX 

The ADC Sequencer drivers last device ID.

Definition at line 382 of file netx_drv_csp_netx90_app.h.

enum DRV_DMAC_PERIPHERAL_E
Enumerator
DRV_DMAC_PERIPHERAL_UART_SHARED_RX 
DRV_DMAC_PERIPHERAL_UART_SHARED_TX 
DRV_DMAC_PERIPHERAL_UART_APP_RX 
DRV_DMAC_PERIPHERAL_UART_APP_TX 
DRV_DMAC_PERIPHERAL_I2C_APP_MASTER 
DRV_DMAC_PERIPHERAL_I2C_APP_SLAVE 
DRV_DMAC_PERIPHERAL_SPI0_APP_RX 
DRV_DMAC_PERIPHERAL_SPI0_APP_TX 
DRV_DMAC_PERIPHERAL_SPI1_APP_RX 
DRV_DMAC_PERIPHERAL_SPI1_APP_TX 
DRV_DMAC_PERIPHERAL_SPI2_APP_RX 
DRV_DMAC_PERIPHERAL_SPI2_APP_TX 
DRV_DMAC_PERIPHERAL_SQI0_APP_RX 
DRV_DMAC_PERIPHERAL_SQI0_APP_TX 
DRV_DMAC_PERIPHERAL_SQI1_APP_RX 
DRV_DMAC_PERIPHERAL_SQI1_APP_TX 
DRV_DMAC_PERIPHERAL_UART_XPIC_APP_RX 
DRV_DMAC_PERIPHERAL_UART_XPIC_APP_TX 
DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_MASTER 
DRV_DMAC_PERIPHERAL_I2C_XPIC_APP_SLAVE 
DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_RX 
DRV_DMAC_PERIPHERAL_SPI_XPIC_APP_TX 
DRV_DMAC_PERIPHERAL_SQI_RX 
DRV_DMAC_PERIPHERAL_SQI_TX 
DRV_DMAC_PERIPHERAL_ETH_RX 
DRV_DMAC_PERIPHERAL_ETH_TX 
DRV_DMAC_PERIPHERAL_HASH 
DRV_DMAC_PERIPHERAL_AES_IN 
DRV_DMAC_PERIPHERAL_AES_OUT 
DRV_DMAC_PERIPHERAL_NC 
DRV_DMAC_PERIPHERAL_30_RESERVED 
DRV_DMAC_PERIPHERAL_31_RESERVED 
DRV_DMAC_PERIPHERAL_MEMORY 

Definition at line 404 of file netx_drv_csp_netx90_app.h.

enum DRV_I2C_DEVICE_ID_E

The I2C device IDs.

They are used to identify the I2C devices in the driver context.

Enumerator
DRV_I2C_DEVICE_ID_I2C0 

The UART drivers internal id for UART 0.

DRV_I2C_DEVICE_ID_I2C1 

The UART drivers internal id for UART of the XPIC.

DRV_I2C_DEVICE_ID_MIN 

The UART drivers last device ID.

DRV_I2C_DEVICE_ID_MAX 

The UART drivers last device ID.

Definition at line 522 of file netx_drv_csp_netx90_app.h.

enum DRV_SPI_DEVICE_ID_E

The SPI device IDs.

They are used to identify the spi devices in the driver context.

Enumerator
DRV_SPI_DEVICE_ID_DEFAULT 

The SPI drivers internal id for SPI 0.

DRV_SPI_DEVICE_ID_SPI0 

The SPI drivers internal id for SPI 0.

DRV_SPI_DEVICE_ID_SPI1 

The SPI drivers internal id for SPI 1.

DRV_SPI_DEVICE_ID_SPI2 

The SPI drivers internal id for SPI 2.

DRV_SPI_DEVICE_ID_SPI3 

The SPI drivers internal id for SPI of the XPIC.

DRV_SPI_DEVICE_ID_SQI0 

The SPI drivers internal id for SQI SHARED.

DRV_SPI_DEVICE_ID_SQI1 

The SPI drivers internal id for SQI0.

DRV_SPI_DEVICE_ID_SQI2 

The SPI drivers internal id for SQI1.

DRV_SPI_DEVICE_ID_MIN 

The SPI driver minimal value.

DRV_SPI_DEVICE_ID_MAX 

The SPI drivers last device ID.

DRV_SPI_DEVICE_ID_SQI_BORDER 

The border value from were a SPI device is an SQI device.

DRV_SPI_DEVICE_ID_QSPI_BORDER 

The border value from were a SQI device is an QSPI device.

Definition at line 474 of file netx_drv_csp_netx90_app.h.

enum DRV_TIM_DEVICE_ID_E

Enumeration of the available timer IDs.

Enumerator
DRV_TIM_DEVICE_ID_GPIOCNTR0 

GPIO COUNTER 0 ID

DRV_TIM_DEVICE_ID_GPIOCNTR1 

GPIO COUNTER 1 ID

DRV_TIM_DEVICE_ID_GPIOCNTR2 

GPIO COUNTER 2 ID

DRV_TIM_DEVICE_ID_GPIOCNTR_MIN 

GPIO COUNTER MIN ID

DRV_TIM_DEVICE_ID_GPIOCNTR_MAX 

GPIO COINTER MAX ID

DRV_TIM_DEVICE_ID_TIMER0 

ARM TIMER 0 ID

DRV_TIM_DEVICE_ID_TIMER1 

ARM TIMER 1 ID

DRV_TIM_DEVICE_ID_TIMER2 

ARM TIMER 2 ID

DRV_TIM_DEVICE_ID_TIMER_MIN 

ARM TIMER MIN ID

DRV_TIM_DEVICE_ID_TIMER_MAX 

ARM TIMER MIN ID

DRV_TIM_DEVICE_ID_SYSTIMECOMPARE 

SYSTEM TIME COMPARATOR

DRV_TIM_DEVICE_ID_SYSTICK 

ARMSYSTEM TICK

DRV_TIM_DEVICE_ID_SYSTIME_COM 

SYSTIME COM ID

DRV_TIM_DEVICE_ID_SYSTIME_COM_UC 

SYSTIME COM UC ID

DRV_TIM_DEVICE_ID_SYSTIME_APP 

SYSTIME APP ID

DRV_TIM_DEVICE_ID_SYSTIME_MIN 

SYSTIME MIN ID

DRV_TIM_DEVICE_ID_SYSTIME_MAX 

SYSTIME MAX ID

DRV_TIM_DEVICE_ID_MIN 

MIN ID

DRV_TIM_DEVICE_ID_MAX 

MAX ID

Definition at line 337 of file netx_drv_csp_netx90_app.h.

enum DRV_UART_DEVICE_ID_E

The UART device IDs.

They are used to identify the spi devices in the driver context.

Enumerator
DRV_UART_DEVICE_ID_UART0 

The UART drivers internal id for UART of the APP.

DRV_UART_DEVICE_ID_UART1 

The UART drivers internal id for UART of the XPIC.

DRV_UART_DEVICE_ID_UART2 

The UART drivers internal id for UART of the SHARED.

DRV_UART_DEVICE_ID_MIN 

The UART drivers last device ID.

DRV_UART_DEVICE_ID_MAX 

The UART drivers last device ID.

Definition at line 447 of file netx_drv_csp_netx90_app.h.