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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
mmio_ctrl (mmio_ctrl) More...
#include <netx90_app.h>
mmio_ctrl (mmio_ctrl)
Definition at line 13743 of file netx90_app.h.
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< (@ 0xFF401300) mmio_ctrl Structure
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| __IOM uint32_t mmio_ctrl_Type::bf_align0 |
[8..6] bitField alignment value for aeabi compatibility
[31..18] bitField alignment value for aeabi compatibility
Definition at line 13750 of file netx90_app.h.
| __IM uint32_t mmio_ctrl_Type::bf_align0 |
[31..18] bitField alignment value for aeabi compatibility
Definition at line 14504 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::bf_align1 |
[15..11] bitField alignment value for aeabi compatibility
[17..11] bitField alignment value for aeabi compatibility
Definition at line 13755 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::bf_align2 |
[31..19] bitField alignment value for aeabi compatibility
Definition at line 13766 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::line |
[17..0] MMIO output state if related MMIO is in PIO mode. If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
[17..0] Write '1's to set the related MMIO output to high level (when it is in PIO mode and output is enabled). If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17. For read the current value of the programmed output states is returned (i.e. the value of mmio_pio_out_line_cfg0).
[17..0] Write '1's to set the related MMIO output to low level (when it is in PIO mode and output is enabled). If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17. For read the current value of the programmed output states is returned (i.e. the value of mmio_pio_out_line_cfg0).
[17..0] MMIO output enable if related MMIO is in PIO mode. If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17.
[17..0] Write '1's to activate the related MMIO output enable (when it is in PIO mode). If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17. For read the current value of the programmed output enables is returned (i.e. the value of mmio_pio_oe_line_cfg0).
[17..0] Write '1's to clear the related MMIO output enable (when it is in PIO mode). If related MMIO is not in PIO mode, programmed setting is ignored. Bit 0 controls MMIO0, bit 1 controls MMIO1, ... bit 17 controlls MMIO17. For read the current value of the programmed output enables is returned (i.e. the value of mmio_pio_oe_line_cfg0).
Definition at line 14367 of file netx90_app.h.
| __IM uint32_t mmio_ctrl_Type::line |
[17..0] sampled MMIO input state. Does not depend whether MMIO is in PIO mode or not. Bit 0 monitors MMIO0, Bit 1 monitors MMIO1, ... bit 17 monitors MMIO17.
[17..0] Bit 0 shows status of MMIO0, Bit 1 shows status of MMIO1, ... bit 17 shows MMIO17. If the MMIO is the standard function of the netX IO (i.e. the netX pin name is MMIOx), the bit of the related MMIO shows whether the MMIO is in PIO mode or not. If the MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than MMIOx), a PIO function is not available by the MMIO function. In this case the bit of the related MMIO shows whether the MMIO function is selected or not. {
Definition at line 14501 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::mmio0_cfg |
(@ 0x00000000) description too long, please enter short description.
Definition at line 13746 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio0_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio10_cfg |
(@ 0x00000028) Multiplexmatrix Configuration Register for MMIO10 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14089 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio10_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio11_cfg |
(@ 0x0000002C) Multiplexmatrix Configuration Register for MMIO11 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14122 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio11_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio12_cfg |
(@ 0x00000030) Multiplexmatrix Configuration Register for MMIO12 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14155 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio12_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio13_cfg |
(@ 0x00000034) Multiplexmatrix Configuration Register for MMIO13 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14188 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio13_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio14_cfg |
(@ 0x00000038) Multiplexmatrix Configuration Register for MMIO14 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14221 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio14_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio15_cfg |
(@ 0x0000003C) Multiplexmatrix Configuration Register for MMIO15 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14254 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio15_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio16_cfg |
(@ 0x00000040) Multiplexmatrix Configuration Register for MMIO16 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14287 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio16_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio17_cfg |
(@ 0x00000044) Multiplexmatrix Configuration Register for MMIO17 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection i
Definition at line 14320 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio17_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio1_cfg |
(@ 0x00000004) Multiplexmatrix Configuration Register for MMIO1 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13771 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio1_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio2_cfg |
(@ 0x00000008) Multiplexmatrix Configuration Register for MMIO2 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13807 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio2_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio3_cfg |
(@ 0x0000000C) Multiplexmatrix Configuration Register for MMIO3 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13843 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio3_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio4_cfg |
(@ 0x00000010) Multiplexmatrix Configuration Register for MMIO4 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13879 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio4_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio5_cfg |
(@ 0x00000014) Multiplexmatrix Configuration Register for MMIO5 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13915 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio5_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio6_cfg |
(@ 0x00000018) Multiplexmatrix Configuration Register for MMIO6 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13951 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio6_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio7_cfg |
(@ 0x0000001C) Multiplexmatrix Configuration Register for MMIO7 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 13987 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio7_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio8_cfg |
(@ 0x00000020) Multiplexmatrix Configuration Register for MMIO8 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 14023 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio8_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio9_cfg |
(@ 0x00000024) Multiplexmatrix Configuration Register for MMIO9 ----------------------------— Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence: 1.: read out access-key from asic_ctrl_access_key register 2.: write back access-key to asic_ctrl_access_key register 3.: write desired value to this register ----------------------------— Core-inputs not mapped to any MMIO will be assigned to 0. If one core-connection is
Definition at line 14056 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio9_cfg_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_in_inv |
[10..10] 1: invert input signal; 0: keep original signal polarity (access-key-protected)
Definition at line 13753 of file netx90_app.h.
| __IM uint32_t mmio_ctrl_Type::mmio_in_line_status0 |
(@ 0x00000060) MMIO input line register of MMIO 0 to 17.
Definition at line 14498 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_in_line_status0_b |
| __IM uint32_t mmio_ctrl_Type::mmio_is_pio_status0 |
(@ 0x00000064) MMIO mode line register of MMIO 0 to 17. Note: PIO Mode can be enabled or disabled in mmio_cfg registers. Note MMIO8 is not a standard-function MMIO and has no PIO function. When bit 8 is set, MMIO8-function will be active on HIF_D8. MMIO9 is not a standard-function MMIO and has no PIO function. When bit 9 is set, MMIO9-function will be active on HIF_D9. MMIO10 is not a standard-function MMIO and has no PIO function. When bit 10 is set, MMIO10-function will be active on HIF_D10.
Definition at line 14509 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_is_pio_status0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_out_inv |
[9..9] 1: invert output signal; 0: keep original signal polarity (access-key-protected)
Definition at line 13751 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_oe_line_cfg0 |
(@ 0x00000054) MMIO PIO line output enable register of MMIO 0 to 17. Changing bits here will change 'pio_oe' bit of related mmio*_cfg register. Changes there will change related bit inside this register. Note: This register is not protected by netX access-key algorithm. Note MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored. MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored. MMIO10 has no PIO function. The value of bit 1
Definition at line 14425 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_oe_line_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_oe_line_reset_cfg0 |
(@ 0x0000005C) MMIO PIO line output enable reset register of MMIO 0 to 17. This register is for deactivating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_oe_line_cfg0' register no read-modify-write sequence (which could be interrupted) is required. Writing '1's here will clear the 'pio_oe' bit of related 'mmio*_cfg' register and also clear the related bits in the 'mmio_pio_oe_line_cfg0' register. For read this register returns the same value as the 'mmio_pio_oe_line_cfg0' regis
Definition at line 14473 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_oe_line_reset_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_oe_line_set_cfg0 |
(@ 0x00000058) MMIO PIO line output enable set register of MMIO 0 to 17. This register is for activating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_oe_line_cfg0' register no read-modify-write sequence (which could be interrupted) is required. Writing '1's here will activate the 'pio_oe' bit of related 'mmio*_cfg' register and also activate the related bits in the 'mmio_pio_oe_line_cfg0' register. For read this register returns the same value as the 'mmio_pio_oe_line_cfg0' reg
Definition at line 14448 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_oe_line_set_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_out_line_cfg0 |
(@ 0x00000048) MMIO PIO line output level register of MMIO 0 to 17. Changing bits here will change 'pio_out' bit of related mmio*_cfg register. Changes there will change related bit inside this register. Note: This register is not protected by netX access-key algorithm. Note MMIO8 has no PIO function. The value of bit 8 of (assotiated with MMIO8) will be ignored. MMIO9 has no PIO function. The value of bit 9 of (assotiated with MMIO9) will be ignored. MMIO10 has no PIO function. The value of bit 1
Definition at line 14353 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_out_line_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_out_line_reset_cfg0 |
(@ 0x00000050) MMIO PIO line output level reset register of MMIO 0 to 17. This register is for deactivating single MMIO PIOs with a single access. In contrast to using the 'mmio_pio_out_line_cfg0' register no read-modify-write sequence (which could be interrupted) is required. Writing '1's here will clear the 'pio_out' bit of related 'mmio*_cfg' register and also clear the related bits in the 'mmio_pio_out_line_cfg0' register. For read this register returns the same value as the 'mmio_pio_out_line_cfg0' re
Definition at line 14400 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_out_line_reset_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_pio_out_line_set_cfg0 |
(@ 0x0000004C) MMIO PIO line output level set register of MMIO 0 to 17. This register is for setting single MMIO PIOs to high level with a single access. In contrast to using the 'mmio_pio_out_line_cfg0' register no read-modify-write sequence (which could be interrupted) is required. Writing '1's here will activate the 'pio_out' bit of related 'mmio*_cfg' register and also activate the related bits in the 'mmio_pio_out_line_cfg0' register. For read this register returns the same value as the 'mmio_pio_out_
Definition at line 14376 of file netx90_app.h.
| struct { ... } mmio_ctrl_Type::mmio_pio_out_line_set_cfg0_b |
| __IOM uint32_t mmio_ctrl_Type::mmio_sel |
[5..0] mmio0 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio1 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio2 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio3 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio4 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio5 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio6 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio7 signal selection (default: PIO mode, access-key-protected).
[5..0] mmio8 signal selection and multiplex function enable (access-key-protected). mmio8 signal is a multiplex option of HIF_D8 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio8 signal. Default value 0x3f deselects mmio8 multiplex option.
[5..0] mmio9 signal selection and multiplex function enable (access-key-protected). mmio9 signal is a multiplex option of HIF_D9 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio9 signal. Default value 0x3f deselects mmio9 multiplex option.
[5..0] mmio10 signal selection and multiplex function enable (access-key-protected). mmio10 signal is a multiplex option of HIF_D10 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio10 signal. Default value 0x3f deselects mmio10 multiplex option.
[5..0] mmio11 signal selection and multiplex function enable (access-key-protected). mmio11 signal is a multiplex option of HIF_D11 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio11 signal. Default value 0x3f deselects mmio11 multiplex option.
[5..0] mmio12 signal selection and multiplex function enable (access-key-protected). mmio12 signal is a multiplex option of HIF_D12 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio12 signal. Default value 0x3f deselects mmio12 multiplex option.
[5..0] mmio13 signal selection and multiplex function enable (access-key-protected). mmio13 signal is a multiplex option of HIF_D13 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio13 signal. Default value 0x3f deselects mmio13 multiplex option.
[5..0] mmio14 signal selection and multiplex function enable (access-key-protected). mmio14 signal is a multiplex option of HIF_D14 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio14 signal. Default value 0x3f deselects mmio14 multiplex option.
[5..0] mmio15 signal selection and multiplex function enable (access-key-protected). mmio15 signal is a multiplex option of HIF_D15 and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio15 signal. Default value 0x3f deselects mmio15 multiplex option.
[5..0] mmio16 signal selection and multiplex function enable (access-key-protected). mmio16 signal is a multiplex option of HIF_RDN and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio16 signal. Default value 0x3f deselects mmio16 multiplex option.
[5..0] mmio17 signal selection and multiplex function enable (access-key-protected). mmio17 signal is a multiplex option of HIF_DIRQ and will be selected when this bit-field is programmed to non-PIO MMIO function. PIO mode does not exist for this mmio17 signal. Default value 0x3f deselects mmio17 multiplex option.
Definition at line 13749 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::pio_oe |
[16..16] PIO mode output enable of mmio0, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio1, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio2, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio3, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio4, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio5, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio6, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
[16..16] PIO mode output enable of mmio7, could also be programmd by mmio_pio_oe_line_cfg register (not protected) Changing this bit will also change according bit in 'mmio_pio_oe_line_cfg register'.
Definition at line 13756 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::pio_out |
[17..17] PIO mode output drive level of mmio0, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio1, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio2, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio3, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio4, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio5, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio6, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
[17..17] PIO mode output drive level of mmio7, could also be programmd by 'mmio_pio_out_line_cfg' register (not protected) Changing this bit will also change according bit in 'mmio_pio_out_line_cf register'.
Definition at line 13760 of file netx90_app.h.
| __IOM uint32_t mmio_ctrl_Type::status_in_ro |
[18..18] current input status of mmio0, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio1, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio2, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio3, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio4, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio5, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio6, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio7, could also be read from 'mmio_in_line_status' register
[18..18] current input status of mmio8 port HIF_D8. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio9 port HIF_D9. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio10 port HIF_D10. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio11 port HIF_D11. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio12 port HIF_D12. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio13 port HIF_D13. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio14 port HIF_D14. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio15 port HIF_D15. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio16 port HIF_RDN. Could also be read from mmio_in_line_status register
[18..18] current input status of mmio17 port HIF_DIRQ. Could also be read from mmio_in_line_status register
Definition at line 13764 of file netx90_app.h.
1.8.11