Hilscher netX microcontroller driver  V0.0.5.0
Documentation of the netX driver package
netx_drv_adc.c
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1 /*!************************************************************************/
24 #include "netx_drv.h"
25 #ifdef DRV_ADC_MODULE_ENABLED
26 
27 /*lint -save -e685 */
28 /*lint -save -e568 */
29 
56 
63 
70 
77 
89 {
90  DRV_STATUS_E eRet = DRV_OK;
91 
92  if(ptDriver == NULL)
93  {
94  return DRV_ERROR_PARAM;
95  }
96  ptDriver->tLock = DRV_LOCK_INITIALIZER;
97  DRV_LOCK(ptDriver);
99  {
100  return DRV_ERROR_PARAM;
101  }
103  {
104  return DRV_ERROR_PARAM;
105  }
108  {
109  return DRV_ERROR_PARAM;
110  }
113  {
114  return DRV_ERROR_PARAM;
115  }
118  {
119  return DRV_ERROR_PARAM;
120  }
123  {
124  return DRV_ERROR_PARAM;
125  }
126 
127  ptDriver->ptDevice = s_apDeviceAddressTable[0];
128 
129  /* madc_cfg */
130  ptDriver->ptDevice->madc_cfg_b.adcclk_period = ptDriver->tConfiguration.eAdcClckPeriod;
131 
132  /* madc_adc01_static_cfg */
133  ptDriver->ptDevice->madc_adc01_static_cfg_b.vref_buffer_enable = ptDriver->tConfiguration.eVrefBufferEnable;
134  ptDriver->ptDevice->madc_adc01_static_cfg_b.adc01_reset_n = ptDriver->tConfiguration.tStaticCfg01.eSoftReset;
135  ptDriver->ptDevice->madc_adc01_static_cfg_b.adc01_enable = ptDriver->tConfiguration.tStaticCfg01.ePowerDown;
136 
137  /* madc_adc23_static_cfg */
138  ptDriver->ptDevice->madc_adc23_static_cfg_b.adc23_reset_n = ptDriver->tConfiguration.tStaticCfg23.eSoftReset;
139  ptDriver->ptDevice->madc_adc23_static_cfg_b.adc23_enable = ptDriver->tConfiguration.tStaticCfg23.ePowerDown;
140 
141  DRV_UNLOCK(ptDriver);
142  return eRet;
143 }
144 
155 {
156  if(ptDriver == NULL)
157  {
158  return DRV_ERROR_PARAM;
159  }
160  DRV_LOCK(ptDriver);
161  size_t iterator;
162  for(iterator = 0; iterator < DRV_ADC_DEVICE_COUNT; iterator++)
163  {
164  if(ptDriver->aptAdcSequencer[iterator] != NULL)
165  {
166  return DRV_BUSY;
167  }
168  }
169  *ptDriver = (DRV_ADC_HANDLE_T ) { 0 };
170  return DRV_OK;
171 }
172 
184 {
185  if(ptDriver == NULL)
186  {
187  return DRV_ERROR_PARAM;
188  }
189 
190  DRV_LOCK(ptDriver);
191 
192  if((eSequencerMask > DRV_ADC_SEQ_DEVICE_MSK_MAX) || (eSequencerMask < DRV_ADC_SEQ_DEVICE_MSK_MIN))
193  {
194  return DRV_ERROR_PARAM;
195  }
196  //TODO: Make use of DRV_ADC_SEQ_DEVICE_COUNT or DRV_ADC_SEQ_DEVICE_ID_MAX/MIN
197  if(eSequencerMask && DRV_ADC_SEQ_DEVICE_MSK_0)
198  {
199  if(ptDriver->aptAdcSequencer[0] != NULL)
200  {
202  {
203  if(ptDriver->aptAdcSequencer[0]->tBuffer.fEnable == true)
204  {
205  ptDriver->aptAdcSequencer[0]->tBuffer.ulPosition = 0;
206  }
208  {
209  ptDriver->aptAdcSequencer[0]->ptDevice->madc_seq_irq_raw = 0x1FFul;
210  ptDriver->aptAdcSequencer[0]->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
211  }
212  else
213  {
214  ptDriver->aptAdcSequencer[0]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
215  }
216  }
217  else
218  {
219  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_0));
220  }
221  }
222  else
223  {
224  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_0));
225  }
226  }
227 
228  if(eSequencerMask && DRV_ADC_SEQ_DEVICE_MSK_1)
229  {
230  if(ptDriver->aptAdcSequencer[1] != NULL)
231  {
233  {
234  if(ptDriver->aptAdcSequencer[1]->tBuffer.fEnable == true)
235  {
236  ptDriver->aptAdcSequencer[1]->tBuffer.ulPosition = 0;
237  }
239  {
240  ptDriver->aptAdcSequencer[1]->ptDevice->madc_seq_irq_raw = 0x1FFul;
241  ptDriver->aptAdcSequencer[1]->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
242  }
243  else
244  {
245  ptDriver->aptAdcSequencer[1]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
246  }
247  }
248  else
249  {
250  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_1));
251  }
252  }
253  else
254  {
255  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_1));
256  }
257  }
258 
259  if(eSequencerMask && DRV_ADC_SEQ_DEVICE_MSK_2)
260  {
261  if(ptDriver->aptAdcSequencer[2] != NULL)
262  {
264  {
265  if(ptDriver->aptAdcSequencer[2]->tBuffer.fEnable == true)
266  {
267  ptDriver->aptAdcSequencer[2]->tBuffer.ulPosition = 0;
268  }
270  {
271  ptDriver->aptAdcSequencer[2]->ptDevice->madc_seq_irq_raw = 0x1FFul;
272  ptDriver->aptAdcSequencer[2]->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
273  }
274  else
275  {
276  ptDriver->aptAdcSequencer[2]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
277  }
278  }
279  else
280  {
281  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_2));
282  }
283  }
284  else
285  {
286  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_2));
287  }
288  }
289 
290  if(eSequencerMask && DRV_ADC_SEQ_DEVICE_MSK_3)
291  {
292  if(ptDriver->aptAdcSequencer[3] != NULL)
293  {
295  {
296  if(ptDriver->aptAdcSequencer[3]->tBuffer.fEnable == true)
297  {
298  ptDriver->aptAdcSequencer[3]->tBuffer.ulPosition = 0;
299  }
301  {
302  ptDriver->aptAdcSequencer[3]->ptDevice->madc_seq_irq_raw = 0x1FFul;
303  ptDriver->aptAdcSequencer[3]->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
304  }
305  else
306  {
307  ptDriver->aptAdcSequencer[3]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
308  }
309  }
310  else
311  {
312  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_3));
313  }
314  }
315  else
316  {
317  eSequencerMask = (DRV_ADC_SEQ_DEVICE_MSK_E) ((uint32_t) eSequencerMask & ~((uint32_t) DRV_ADC_SEQ_DEVICE_MSK_3));
318  }
319  }
320 
321  /* start all together */
322  ptDriver->ptDevice->madc_start = (uint32_t) eSequencerMask;
323 
324  DRV_UNLOCK(ptDriver);
325  return DRV_OK;
326 }
327 
339 {
340  if(ptDriver == NULL)
341  {
342  return DRV_ERROR_PARAM;
343  }
344 
345  DRV_LOCK(ptDriver);
346 
347  if((eSequencerMask > DRV_ADC_SEQ_DEVICE_MSK_MAX) || (eSequencerMask < DRV_ADC_SEQ_DEVICE_MSK_MIN))
348  {
349  DRV_UNLOCK(ptDriver);
350  return DRV_ERROR_PARAM;
351  }
352 
353  if(eSequencerMask & (unsigned int) DRV_ADC_SEQ_DEVICE_MSK_0)
354  {
356 
358  {
359  ptDriver->aptAdcSequencer[0]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
360  }
361  }
362 
363  if(eSequencerMask & (unsigned int) DRV_ADC_SEQ_DEVICE_MSK_1)
364  {
366 
368  {
369  ptDriver->aptAdcSequencer[1]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
370  }
371  }
372 
373  if(eSequencerMask & (unsigned int) DRV_ADC_SEQ_DEVICE_MSK_2)
374  {
376 
378  {
379  ptDriver->aptAdcSequencer[2]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
380  }
381  }
382 
383  if(eSequencerMask & (unsigned int) DRV_ADC_SEQ_DEVICE_MSK_3)
384  {
386 
388  {
389  ptDriver->aptAdcSequencer[3]->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
390  }
391  }
392 
393  ptDriver->ptDevice->madc_start = (uint32_t) eSequencerMask;
394 
395  DRV_UNLOCK(ptDriver);
396  return DRV_OK;
397 }
398 
410 {
411  DRV_STATUS_E eRet = DRV_OK;
412  uint32_t ulIndexLoop;
413 
414  if((ptDriver == NULL) || (ptSequencer == NULL))
415  {
416  return DRV_ERROR_PARAM;
417  }
418  ptSequencer->tLock = DRV_LOCK_INITIALIZER;
419  DRV_LOCK(ptSequencer);
420 
422  {
423  return DRV_ERROR_PARAM;
424  }
425  else
426  {
427  ptSequencer->ptDevice = s_apSubDeviceAddressTable[(uint32_t) ptSequencer->tConfiguration.eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN];
428  s_apHandleAddressTable[(uint32_t) ptSequencer->tConfiguration.eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN] = ptSequencer;
429  ptDriver->aptAdcSequencer[(uint32_t) ptSequencer->tConfiguration.eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN] = ptSequencer;
430  ptSequencer->ptParent = ptDriver;
431  }
433  {
434  return DRV_ERROR_PARAM;
435  }
438  {
439  return DRV_ERROR_PARAM;
440  }
442  {
443  return DRV_ERROR_PARAM;
444  }
446  {
447  return DRV_ERROR_PARAM;
448  }
450  {
451  return DRV_ERROR_PARAM;
452  }
454  {
455  return DRV_ERROR_PARAM;
456  }
458  {
459  return DRV_ERROR_PARAM;
460  }
461  for(ulIndexLoop = 0; ulIndexLoop < DRV_ADC_INPUTS_MAX; ulIndexLoop++)
462  {
465  {
466  return DRV_ERROR_PARAM;
467  }
468  }
470  {
471  return DRV_ERROR_PARAM;
472  }
473  for(ulIndexLoop = 0; ulIndexLoop < DRV_ADC_MEASUREMENTS_MAX; ulIndexLoop++)
474  {
475  if((ptSequencer->tConfiguration.tMeasurement[ulIndexLoop].eEnable > DRV_ADC_SEQ_MEAS_ENABLE_MAX)
476  || (ptSequencer->tConfiguration.tMeasurement[ulIndexLoop].eEnable < DRV_ADC_SEQ_MEAS_ENABLE_MIN))
477  {
478  return DRV_ERROR_PARAM;
479  }
482  {
483  return DRV_ERROR_PARAM;
484  }
487  {
488  return DRV_ERROR_PARAM;
489  }
492  {
493  return DRV_ERROR_PARAM;
494  }
495  if((ptSequencer->tConfiguration.tMeasurement[ulIndexLoop].eTrigger > DRV_ADC_SEQ_MEAS_TRIGGER_MAX)
496  || (ptSequencer->tConfiguration.tMeasurement[ulIndexLoop].eTrigger < DRV_ADC_SEQ_MEAS_TRIGGER_MIN))
497  {
498  return DRV_ERROR_PARAM;
499  }
500  }
501 
502  /* madc_seq_cfg */
503  if(ptSequencer->tConfiguration.eOperationMode == DRV_OPERATION_MODE_POLL) /* Pooling mode, DMA is always disable */
504  {
506  }
507  else if(ptSequencer->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA) /* DMA mode, DMA is always enable */
508  {
510  }
511 
512  ptSequencer->ptDevice->madc_seq_cfg_b.dma_disable = ptSequencer->tConfiguration.eDmaModeDisable;
513  ptSequencer->ptDevice->madc_seq_cfg_b.dma_32bit_adr = ptSequencer->tConfiguration.e32BitMode;
514  ptSequencer->ptDevice->madc_seq_cfg_b.vref_vdd3 = ptSequencer->tConfiguration.eVrefVdd3;
515  ptSequencer->ptDevice->madc_seq_cfg_b.adcclk_sync = ptSequencer->tConfiguration.eClkSync;
516  ptSequencer->ptDevice->madc_seq_cfg_b.adcclk_phase = ptSequencer->tConfiguration.eClkPhase;
517  ptSequencer->ptDevice->madc_seq_cfg_b.adcclk_period = ptSequencer->tConfiguration.eClkPeriod;
518 
519  /* madc_seq_ms_en */
528 
529  /* madc_seq_m0 */
534 
535  /* madc_seq_m1 */
540 
541  /* madc_seq_m2 */
546 
547  /* madc_seq_m3 */
552 
553  /* madc_seq_m4 */
558 
559  /* madc_seq_m5 */
564 
565  /* madc_seq_m6 */
570 
571  /* madc_seq_m7 */
576 
577  /* madc_seq_tracking_time_muxx */
586 
587  /* madc_seq_ms_baseadr */
588  ptSequencer->ptDevice->madc_seq_ms_baseadr = (uint32_t) ptSequencer->tConfiguration.eBaseAdr;
589 
591  {
593  DRV_NVIC_EnableIRQ(s_apHandleIRQnTable[(uint32_t) ptSequencer->tConfiguration.eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN]);
594 
595  ptSequencer->ptDevice->madc_seq_irq_raw = 0x1FFul;
596  ptSequencer->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
597  }
598 
599  DRV_UNLOCK(ptSequencer);
600  return eRet;
601 }
602 
613 {
614  if(ptSequencer == NULL)
615  {
616  return DRV_ERROR_PARAM;
617  }
618  DRV_LOCK(ptSequencer);
619  if(ptSequencer->ptParent->aptAdcSequencer[ptSequencer->tConfiguration.eDeviceID - (unsigned int) DRV_ADC_SEQ_DEVICE_ID_MIN] != ptSequencer)
620  {
621  return DRV_ERROR;
622  }
623  else
624  {
625  ptSequencer->ptParent->aptAdcSequencer[ptSequencer->tConfiguration.eDeviceID - (unsigned int) DRV_ADC_SEQ_DEVICE_ID_MIN] = NULL;
626  }
628  {
630  ptSequencer->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
631  DRV_NVIC_ClearPendingIRQ(s_apHandleIRQnTable[(uint32_t) ptSequencer->tConfiguration.eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN]);
632  ptSequencer->ptDevice->madc_seq_irq_raw = 0x1FFul;
633  }
634  *ptSequencer = (DRV_ADC_SEQ_HANDLE_T ) { 0 };
635  return DRV_OK;
636 }
637 
649 {
650  if(ptSequencer == NULL)
651  {
652  return DRV_ERROR_PARAM;
653  }
654 
655  DRV_LOCK(ptSequencer);
656 
658  {
659  DRV_UNLOCK(ptSequencer);
660  return DRV_ERROR_PARAM;
661  }
662 
663  ptSequencer->tConfiguration.eContinuousMode = eMode;
664 
665  DRV_UNLOCK(ptSequencer);
666  return DRV_OK;
667 }
668 
679 {
680  if(ptSequencer == NULL)
681  {
682  return DRV_ERROR_PARAM;
683  }
684 
685  if(ptSequencer->ptDevice == NULL)
686  {
687  return DRV_ERROR_PARAM;
688  }
689 
690  DRV_LOCK(ptSequencer);
691 
692  if(ptSequencer->tBuffer.fEnable)
693  {
694  ptSequencer->tBuffer.ulPosition = 0ul;
695  }
696 
698  {
699  ptSequencer->ptDevice->madc_seq_irq_raw = 0x1FFul;
700  ptSequencer->ptDevice->madc_seq_irq_mask_set = 0x1FFul;
701  }
702  else
703  {
704  ptSequencer->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
705  }
706 
707  ptSequencer->ptDevice->madc_seq_cmd_b.continuous = ptSequencer->tConfiguration.eContinuousMode;
708  ptSequencer->ptDevice->madc_seq_cmd_b.run = 1u;
709 
710  DRV_UNLOCK(ptSequencer);
711  return DRV_OK;
712 }
713 
724 {
725  if(ptSequencer == NULL)
726  {
727  return DRV_ERROR_PARAM;
728  }
729 
730  DRV_LOCK(ptSequencer);
731 
732  ptSequencer->ptDevice->madc_seq_cmd_b.run = 0u;
733 
735  {
736  ptSequencer->ptDevice->madc_seq_irq_mask_reset = 0x1FFul;
737  }
738 
739  DRV_UNLOCK(ptSequencer);
740  return DRV_OK;
741 }
742 
753 {
754  if(ptSequencer == NULL)
755  {
756  return DRV_ERROR_PARAM;
757  }
758 
759  DRV_LOCK(ptSequencer);
760 
761  ptSequencer->tBuffer.fEnable = false;
762  ptSequencer->ptDevice->madc_seq_cmd_b.reset = 1u;
763 
764  DRV_UNLOCK(ptSequencer);
765  return DRV_OK;
766 }
767 
783 {
784  uint32_t ulMadc_Seq_Mx = 0ul;
785 
786  if(ptSequencer == NULL)
787  {
788  return DRV_ERROR_PARAM;
789  }
790 
791  DRV_LOCK(ptSequencer);
792 
793  if((eMeasurement > DRV_ADC_SEQ_MEASUREMENT_MAX) || (eMeasurement < DRV_ADC_SEQ_MEASUREMENT_MIN))
794  {
795  DRV_UNLOCK(ptSequencer);
796  return DRV_ERROR_PARAM;
797  }
798 
799  if((eInputChannel > DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MAX) || (eInputChannel < DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MIN))
800  {
801  DRV_UNLOCK(ptSequencer);
802  return DRV_ERROR_PARAM;
803  }
804 
805  if((eOversampling > DRV_ADC_SEQ_MEAS_OVERSAMPLING_MAX) || (eOversampling < DRV_ADC_SEQ_MEAS_OVERSAMPLING_MIN))
806  {
807  DRV_UNLOCK(ptSequencer);
808  return DRV_ERROR_PARAM;
809  }
810 
811  if((eTrigger > DRV_ADC_SEQ_MEAS_TRIGGER_MAX) || (eTrigger < DRV_ADC_SEQ_MEAS_TRIGGER_MIN))
812  {
813  DRV_UNLOCK(ptSequencer);
814  return DRV_ERROR_PARAM;
815  }
816 
817  ulMadc_Seq_Mx = ((eInputChannel << madc_seq0_madc_seq_m0_mux_Pos) & madc_seq0_madc_seq_m0_mux_Msk)
820 
821  switch (eMeasurement)
822  {
824  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m0 & madc_seq0_madc_seq_m0_adr_offset_Msk);
825  ptSequencer->ptDevice->madc_seq_m0 = ulMadc_Seq_Mx;
826  break;
828  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m1 & madc_seq0_madc_seq_m1_adr_offset_Msk);
829  ptSequencer->ptDevice->madc_seq_m1 = ulMadc_Seq_Mx;
830  break;
832  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m2 & madc_seq0_madc_seq_m2_adr_offset_Msk);
833  ptSequencer->ptDevice->madc_seq_m2 = ulMadc_Seq_Mx;
834  break;
836  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m3 & madc_seq0_madc_seq_m3_adr_offset_Msk);
837  ptSequencer->ptDevice->madc_seq_m3 = ulMadc_Seq_Mx;
838  break;
840  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m4 & madc_seq0_madc_seq_m4_adr_offset_Msk);
841  ptSequencer->ptDevice->madc_seq_m4 = ulMadc_Seq_Mx;
842  break;
844  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m5 & madc_seq0_madc_seq_m5_adr_offset_Msk);
845  ptSequencer->ptDevice->madc_seq_m5 = ulMadc_Seq_Mx;
846  break;
848  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m6 & madc_seq0_madc_seq_m6_adr_offset_Msk);
849  ptSequencer->ptDevice->madc_seq_m6 = ulMadc_Seq_Mx;
850  break;
852  ulMadc_Seq_Mx |= (ptSequencer->ptDevice->madc_seq_m7 & madc_seq0_madc_seq_m7_adr_offset_Msk);
853  ptSequencer->ptDevice->madc_seq_m7 = ulMadc_Seq_Mx;
854  break;
855  default:
856  DRV_UNLOCK(ptSequencer);
857  return DRV_ERROR_PARAM;
858  }
859  DRV_UNLOCK(ptSequencer);
860  return DRV_OK;
861 }
862 
875 {
876  uint32_t Madc_Seq_Status = 0ul;
877 
878  if(ptSequencer == NULL)
879  {
880  return DRV_ERROR_PARAM;
881  }
882 
883  /* important: read full sequencer status with one access */
884  Madc_Seq_Status = ptSequencer->ptDevice->madc_seq_status;
885 
886  ptState->ulHalfClockCycle = (uint8_t) ((Madc_Seq_Status & madc_seq1_madc_seq_status_adc_half_clock_cycle_Msk)
890 
891  if(ptState->ulHalfClockCycle == 0)
892  {
893  return DRV_OK;
894  }
895  return DRV_BUSY;
896 }
897 
912 DRV_STATUS_E DRV_ADC_Seq_GetSample(DRV_ADC_SEQ_HANDLE_T * const ptSequencer, uint32_t* const pulSample, uint8_t* const pbMeasNr)
913 {
914  uint32_t Madc_Seq_Result_Current = 0ul;
915 
916  if(ptSequencer == NULL)
917  {
918  return DRV_ERROR_PARAM;
919  }
920 
921  DRV_LOCK(ptSequencer);
922 
923  /* important: read full sequencer result with one access */
924  Madc_Seq_Result_Current = ptSequencer->ptDevice->madc_seq_result_current;
925 
926  if(pulSample != NULL)
927  {
929  }
930 
931  if(pbMeasNr != NULL)
932  {
934  }
935 
936  if(Madc_Seq_Result_Current & madc_seq1_madc_seq_result_current_valid_Msk)
937  {
938  DRV_UNLOCK(ptSequencer);
939  return DRV_OK;
940  }
941  else
942  {
943  DRV_UNLOCK(ptSequencer);
944  return DRV_BUSY;
945  }
946 }
947 
960 DRV_STATUS_E DRV_ADC_Seq_GetLastSample(DRV_ADC_SEQ_HANDLE_T * const ptSequencer, uint32_t* const pulSample, uint8_t* const pbMeasNr)
961 {
962  uint32_t Madc_Seq_Result_Last = 0ul;
963 
964  if(ptSequencer == NULL)
965  {
966  return DRV_ERROR_PARAM;
967  }
968 
969  DRV_LOCK(ptSequencer);
970 
971  /* important: read full sequencer last result with one access */
972  Madc_Seq_Result_Last = ptSequencer->ptDevice->madc_seq_result_last;
973 
974  if(pulSample != NULL)
975  {
977  }
978 
979  if(pbMeasNr != NULL)
980  {
982  }
983 
984  if(Madc_Seq_Result_Last & madc_seq1_madc_seq_result_last_valid_Msk)
985  {
986  DRV_UNLOCK(ptSequencer);
987  return DRV_OK;
988  }
989  else
990  {
991  DRV_UNLOCK(ptSequencer);
992  return DRV_BUSY;
993  }
994 }
995 
1015 DRV_STATUS_E DRV_ADC_Seq_SetSampleSeriesBuffer(DRV_ADC_SEQ_HANDLE_T * const ptSequencer, uint16_t* pulSampleSeries, size_t tSize,
1016  DRV_CALLBACK_F fnCallback, void* pUser)
1017 {
1018  if((ptSequencer == NULL) || (pulSampleSeries == NULL) || (tSize < 2))
1019  {
1020  return DRV_ERROR_PARAM;
1021  }
1022 
1024  {
1025  return DRV_NSUPP; /* buffer functions only supported in interrupt mode */
1026  }
1027  DRV_LOCK(ptSequencer);
1028 
1029  ptSequencer->tBuffer.fEnable = true;
1030  ptSequencer->tBuffer.pvBufferAdr = (void*) pulSampleSeries;
1031  ptSequencer->tBuffer.ulPosition = 0;
1032  ptSequencer->tBuffer.ulMaxCount = (uint32_t) (tSize / 2);
1033  ptSequencer->tBuffer.fnWrapCallback = fnCallback;
1034  ptSequencer->tBuffer.pWrapCallbackkHandle = pUser;
1035 
1036  DRV_UNLOCK(ptSequencer);
1037  return DRV_OK;
1038 }
1039 
1050 {
1051  uint32_t ulRawValue;
1052  uint16_t* pusSample;
1053 
1054  /* If buffer mode active, try to save the result */
1055  if(ptSequencer->tBuffer.fEnable)
1056  {
1057  ulRawValue = ptSequencer->ptDevice->madc_seq_result_current;
1058  pusSample = (uint16_t*) ptSequencer->tBuffer.pvBufferAdr + ptSequencer->tBuffer.ulPosition;
1059 
1060  /* Check if the result valid and assigned to this measurement.
1061  * Only the case if this measurement be the last in the sequence or the next is not be triggered yet */
1062  if(ulRawValue & (0x80000000 + (eMeasurement << madc_seq0_madc_seq_result_current_mnr_Pos)))
1063  {
1064  *pusSample = (uint16_t) ulRawValue & madc_seq0_madc_seq_result_current_val_Msk;
1065  }
1066  else
1067  {
1068  /* Get the last latched result */
1069  ulRawValue = ptSequencer->ptDevice->madc_seq_result_last;
1070 
1071  /* Check if the last result valid and assigned to this measurement. */
1072  if(ulRawValue & (0x80000000 + (eMeasurement << madc_seq0_madc_seq_result_last_mnr_Pos)))
1073  {
1074  *pusSample = (uint16_t) ptSequencer->ptDevice->madc_seq_result_last & madc_seq0_madc_seq_result_last_val_Msk;
1075  }
1076  else
1077  {
1078  /* Possible to late and the correct result is overwritten. Possible solution is to activate the DMA mode */
1079  *pusSample = DRV_ADC_SEQ_CATCHED_NO_RESULT;
1080  }
1081  }
1082  ptSequencer->tBuffer.ulPosition++;
1083  if(ptSequencer->tBuffer.ulPosition == ptSequencer->tBuffer.ulMaxCount)
1084  {
1085  /* Last value to the buffer in this round, chance to execute a callback */
1086  if(ptSequencer->tBuffer.fnWrapCallback != 0)
1087  {
1088  ptSequencer->tBuffer.fnWrapCallback((void*) ptSequencer, ptSequencer->tBuffer.pWrapCallbackkHandle);
1089  }
1090  ptSequencer->tBuffer.ulPosition = 0; /* next round for the ring buffer */
1091  }
1092  }
1093  if(ptSequencer->tConfiguration.fnMeasurementCompleteCallback[eMeasurement] != 0)
1094  {
1095  ptSequencer->tConfiguration.fnMeasurementCompleteCallback[eMeasurement]((void*) ptSequencer,
1096  ptSequencer->tConfiguration.pMeasurementCompleteCallbackHandle[eMeasurement]);
1097  }
1098 }
1099 
1112 {
1113  uint32_t ulDeviceOffset = (uint32_t) eDeviceID - (uint32_t) DRV_ADC_SEQ_DEVICE_ID_MIN;
1114 
1115  DRV_ADC_SEQ_HANDLE_T* ptSequencer = s_apHandleAddressTable[ulDeviceOffset];
1116 #ifndef NDEBUG
1117  if(ptSequencer == 0 || ptSequencer->ptDevice != s_apSubDeviceAddressTable[ulDeviceOffset])
1118  {
1119  ((DRV_ADC_SEQ_DEVICE_T * const ) s_apSubDeviceAddressTable[ulDeviceOffset])->madc_seq_ms_en = 0ul;
1120  DRV_NVIC_DisableIRQ(s_apHandleIRQnTable[ulDeviceOffset]);
1121  return;
1122  }
1123 #endif
1124 
1125  uint32_t ulIrqMasked = ptSequencer->ptDevice->madc_seq_irq_mask_reset; /* shows bit number of the lowest active bit in IRQ_MASKED */
1126 
1127  switch (ulIrqMasked)
1128  { /* fall through conditions */
1137  (void) DRV_ACD_IRQ_SaveResult(ptSequencer, (DRV_ADC_SEQ_MEASUREMENT_E) ulIrqMasked);
1138  break;
1140  if(ptSequencer->tConfiguration.fnSequenceCompleteCallback != 0)
1141  {
1142  ptSequencer->tConfiguration.fnSequenceCompleteCallback((void*) ptSequencer, ptSequencer->tConfiguration.pSequenceCompleteCallbackHandle);
1143  }
1144  break;
1145  default:
1146  break;
1147  }
1148  /* Resets the appropriate IRQ */
1149  ptSequencer->ptDevice->madc_seq_irq_raw = 1ul << ulIrqMasked;
1150 }
1151 
1152 #define DRV_ACD_IRQHandler_Generator(id, _) DRV_Default_IRQHandler_Function_Generator(MADC ## id ## _IRQHandler ,DRV_ACD_IRQ_Inline_Handler,DRV_ADC_SEQ_DEVICE_ID_ADC ## id)
1153 
1154 /*lint -save -e123 */
1156 /*lint -restore */
1157 
1158 /* End of group ADC */
1159 
1160 /*lint -restore */
1161 /*lint -restore */
1162 
1163 #endif /* DRV_ADC_MODULE_DISABLE */
#define DRV_ADC_SEQ_DEVICE_IRQ_LIST
#define madc_seq1_madc_seq_result_current_val_Msk
Definition: netx90_app.h:43762
DRV_ADC_STATE_MEASUREMENT_E eActiveMeasurement
Definition: netx_drv_adc.h:461
DRV_CALLBACK_F fnWrapCallback
Definition: netx_drv_adc.h:452
DRV_ADC_SEQ_CONFIGURATION_T tConfiguration
Definition: netx_drv_adc.h:523
#define madc_seq0_madc_seq_m1_adr_offset_Msk
Definition: netx90_app.h:43325
#define DRV_DEF_REPEAT_EVAL(...)
Definition: netx_drv.h:234
struct madc_Type::@4208::@4221 madc_adc01_static_cfg_b
#define madc_seq1_madc_seq_result_current_valid_Msk
Definition: netx90_app.h:43754
struct madc_Type::@4210::@4222 madc_adc23_static_cfg_b
Structure containing the state of the adc sequencer.
Definition: netx_drv_adc.h:459
struct DRV_ADC_HANDLE_Ttag DRV_ADC_HANDLE_T
Type definition of the adc handle structure.
Definition: netx_drv_adc.h:501
DRV_ADC_STATIC_CFG_T tStaticCfg23
Definition: netx_drv_adc.h:540
#define madc_seq1_madc_seq_result_last_valid_Msk
Definition: netx90_app.h:43765
#define madc_seq1_madc_seq_result_current_val_Pos
Definition: netx90_app.h:43761
#define madc_seq0_madc_seq_irq_masked_m5_cmpl_Pos
Definition: netx90_app.h:43499
#define madc_seq0_madc_seq_irq_masked_m7_cmpl_Pos
Definition: netx90_app.h:43495
#define DRV_LOCK_INITIALIZER
Initializer of the type to be locked as rvalue is in default the mutex initializer.
void * pMeasurementCompleteCallbackHandle[DRV_ADC_MEASUREMENTS_MAX]
Definition: netx_drv_adc.h:490
__IOM uint32_t madc_seq_m4
Definition: netx90_app.h:17642
IRQn_Type
Definition: netx90_app.h:57
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E
Input channel multiplexer setting.
Definition: netx_drv_adc.h:280
#define madc_seq1_madc_seq_result_last_val_Msk
Definition: netx90_app.h:43773
__IOM uint32_t madc_seq_tracking_time_mux0
Definition: netx90_app.h:17429
DRV_STATUS_E DRV_ADC_Seq_Init(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_HANDLE_T *const ptDriver)
Initializes the adc sequencer and its handle by the given configuration.
Definition: netx_drv_adc.c:409
void DRV_NVIC_DisableIRQ(IRQn_Type IRQn)
This method disables a given interrupt.
#define DRV_ADC_SEQ_DEVICE_COUNT
DRV_ADC_SEQ_DEVICE_ID_E eDeviceID
Definition: netx_drv_adc.h:474
#define madc_seq0_madc_seq_result_current_mnr_Pos
Definition: netx90_app.h:43421
#define madc_seq0_madc_seq_irq_masked_m0_cmpl_Pos
Definition: netx90_app.h:43509
struct madc_seq0_Type::@4245::@4292 madc_seq_ms_en_b
__IOM uint32_t madc_seq_tracking_time_mux5
Definition: netx90_app.h:17489
__IOM uint32_t madc_seq_m0
Definition: netx90_app.h:17564
#define madc_seq1_madc_seq_status_m_nr_Msk
Definition: netx90_app.h:43751
DRV_STATUS_E DRV_ADC_Seq_Start(DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
Starts the given adc sequencer.
Definition: netx_drv_adc.c:678
struct madc_seq0_Type::@4249::@4294 madc_seq_m0_b
struct madc_seq0_Type::@4227::@4283 madc_seq_cfg_b
DRV_LOCK_T tLock
Definition: netx_drv_adc.h:556
DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_E eChannelTrackingTime[DRV_ADC_INPUTS_MAX]
Definition: netx_drv_adc.h:482
#define madc_seq0_madc_seq_m6_adr_offset_Msk
Definition: netx90_app.h:43380
DRV_ADC_SEQ_MEASUREMENT_E
Measurements of the sequencer.
Definition: netx_drv_adc.h:235
DRV_ADC_HANDLE_T * ptParent
Definition: netx_drv_adc.h:522
struct madc_seq0_Type::@4251::@4295 madc_seq_m1_b
The handle of the driver.
Definition: netx_drv_adc.h:551
void DRV_NVIC_EnableIRQ(IRQn_Type IRQn)
This method enables a given interrupt.
DRV_ADC_DEVICE_T * ptDevice
Definition: netx_drv_adc.h:553
#define DRV_ADC_SEQ_DEVICE_LIST
#define DRV_ADC_MEASUREMENTS_MAX
DRV_STATUS_E DRV_ADC_Seq_GetLastSample(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, uint32_t *const pulSample, uint8_t *const pbMeasNr)
Stores the last sample of the the given adc.
Definition: netx_drv_adc.c:960
DRV_ADC_SEQ_CLK_SYNC_E eClkSync
Definition: netx_drv_adc.h:479
DRV_ADC_SEQ_CONTINUOUS_MODE_E
Continuous or Single Shot mode of the device and api.
Definition: netx_drv_adc.h:345
DRV_ADC_SEQ_MEAS_OVERSAMPLING_E eOversample
Definition: netx_drv_adc.h:439
__IM uint32_t madc_seq_status
Definition: netx90_app.h:17727
DRV_CALLBACK_F fnSequenceCompleteCallback
Definition: netx_drv_adc.h:487
__IOM uint32_t madc_seq_irq_mask_reset
Definition: netx90_app.h:17868
DRV_STATUS_E DRV_ADC_Start(DRV_ADC_HANDLE_T *const ptDriver, DRV_ADC_SEQ_DEVICE_MSK_E eSequencerMask)
Starts the sequencers given by the mask (software trigger).
Definition: netx_drv_adc.c:183
DRV_ADC_SEQ_MEAS_T tMeasurement[DRV_ADC_MEASUREMENTS_MAX]
Definition: netx_drv_adc.h:486
#define madc_seq0_madc_seq_cmd_run_Msk
Definition: netx90_app.h:43408
DRV_STATUS_E DRV_ADC_Seq_GetState(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_STATE_T *const ptState)
Aquires the state of the given adc sequencer.
Definition: netx_drv_adc.c:874
#define madc_seq0_madc_seq_m0_oversample_Pos
Definition: netx90_app.h:43317
__IOM uint32_t madc_seq_m1
Definition: netx90_app.h:17600
DRV_STATUS_E DRV_ADC_Driver_DeInit(DRV_ADC_HANDLE_T *const ptDriver)
Deinitializes the adc device and handle.
Definition: netx_drv_adc.c:154
DRV_ADC_SEQ_32Bit_MODE_E e32BitMode
Definition: netx_drv_adc.h:477
#define DRV_ADC_DEVICE_COUNT
__IOM uint32_t madc_seq_irq_raw
Definition: netx90_app.h:17791
#define DRV_LOCK(__HANDLE__)
A function calling the trylock of the mutex and returning locked in case it is blocked.
static DRV_ADC_DEVICE_T *const s_apDeviceAddressTable[DRV_ADC_DEVICE_COUNT]
Table of the device addresses.
Definition: netx_drv_adc.c:55
DRV_ADC_SEQ_DMA_MODE_E eDmaModeDisable
Definition: netx_drv_adc.h:476
__IM uint32_t madc_seq_result_last
Definition: netx90_app.h:17753
struct madc_seq0_Type::@4261::@4300 madc_seq_m6_b
__IOM uint32_t madc_seq_m6
Definition: netx90_app.h:17670
__IOM uint32_t madc_start
Definition: netx90_app.h:17324
DRV_ADC_SEQ_VREF_VDD3_E eVrefVdd3
Definition: netx_drv_adc.h:478
#define madc_seq0_madc_seq_result_current_val_Msk
Definition: netx90_app.h:43426
__IOM uint32_t madc_seq_m3
Definition: netx90_app.h:17628
__STATIC_INLINE void DRV_ACD_IRQ_SaveResult(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_MEASUREMENT_E const eMeasurement)
#define madc_seq0_madc_seq_irq_masked_m1_cmpl_Pos
Definition: netx90_app.h:43507
#define madc_seq0_madc_seq_irq_masked_seq_cmpl_Pos
Definition: netx90_app.h:43493
DRV_ADC_VREF_BUFFER_E eVrefBufferEnable
Definition: netx_drv_adc.h:538
#define DRV_ADC_INPUTS_MAX
DRV_STATUS_E DRV_ADC_Seq_GetSample(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, uint32_t *const pulSample, uint8_t *const pbMeasNr)
Stores the current acquired sample of the the given adc.
Definition: netx_drv_adc.c:912
__IOM uint32_t madc_seq_irq_mask_set
Definition: netx90_app.h:17838
DRV_ADC_SEQ_MEAS_OVERSAMPLING_E
Number of samples minus one to sum for this measurement i.e. 0:sum 1 samples, 1:sum 2 samples...
Definition: netx_drv_adc.h:297
This file contains all the functions prototypes for the peripheral module driver. ...
#define DRV_ADC_DEVICE_LIST
DRV_ADC_CLK_PERIOD_E eAdcClckPeriod
Definition: netx_drv_adc.h:537
DRV_ADC_SEQ_CLK_PERIOD_E eClkPeriod
Definition: netx_drv_adc.h:481
DRV_STATUS_E DRV_ADC_Stop(DRV_ADC_HANDLE_T *const ptDriver, DRV_ADC_SEQ_DEVICE_MSK_E eSequencerMask)
Stops the sequencers given by the mask.
Definition: netx_drv_adc.c:338
#define madc_seq0_madc_seq_irq_masked_m6_cmpl_Pos
Definition: netx90_app.h:43497
DRV_ADC_SEQ_BASE_ADDRESS_E eBaseAdr
Definition: netx_drv_adc.h:485
DRV_STATUS_E DRV_ADC_Seq_DeInit(DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
Deinitializes the adc sequencer and its handle.
Definition: netx_drv_adc.c:612
static DRV_ADC_SEQ_HANDLE_T * s_apHandleAddressTable[DRV_ADC_SEQ_DEVICE_COUNT]
Used for mapping the handle to an interrupt.
Definition: netx_drv_adc.c:76
static IRQn_Type const s_apHandleIRQnTable[DRV_ADC_SEQ_DEVICE_COUNT]
Table of the IRQ vector numbers.
Definition: netx_drv_adc.c:69
__IOM uint32_t madc_seq_tracking_time_mux7
Definition: netx90_app.h:17509
__IOM uint32_t madc_seq_ms_baseadr
Definition: netx90_app.h:17554
madc (madc)
Definition: netx90_app.h:17265
struct madc_seq0_Type::@4265::@4302 madc_seq_cmd_b
#define DRV_ADC_SEQ_CATCHED_NO_RESULT
Result was not accessible after the measurement.
Definition: netx_drv_adc.h:97
uint8_t ulHalfClockCycle
Definition: netx_drv_adc.h:462
__IOM uint32_t madc_seq_m5
Definition: netx90_app.h:17656
struct madc_seq0_Type::@4263::@4301 madc_seq_m7_b
#define madc_seq0_madc_seq_irq_masked_m3_cmpl_Pos
Definition: netx90_app.h:43503
__IM uint32_t madc_seq_result_current
Definition: netx90_app.h:17740
__IOM uint32_t madc_seq_tracking_time_mux2
Definition: netx90_app.h:17459
DRV_ADC_SEQ_BUFFER_T tBuffer
Definition: netx_drv_adc.h:525
#define madc_seq0_madc_seq_irq_masked_m4_cmpl_Pos
Definition: netx90_app.h:43501
__IOM uint32_t madc_seq_tracking_time_mux4
Definition: netx90_app.h:17479
DRV_ADC_STATE_MEASUREMENT_E
The enumeration for the available measurements.
Definition: netx_drv_adc.h:382
DRV_ADC_POWER_DOWN_E ePowerDown
Definition: netx_drv_adc.h:509
void(* DRV_CALLBACK_F)(void *pvDriverHandle, void *pvUserHandle)
The definition of callbacks used in the driver.
Definition: netx_drv_def.h:48
#define madc_seq0_madc_seq_m0_adr_offset_Msk
Definition: netx90_app.h:43314
DRV_ADC_SEQ_HANDLE_T * aptAdcSequencer[4]
Definition: netx_drv_adc.h:554
#define madc_seq0_madc_seq_irq_masked_m2_cmpl_Pos
Definition: netx90_app.h:43505
struct madc_Type::@4206::@4220 madc_cfg_b
DRV_STATUS_E
DRV Status structures definition.
Definition: netx_drv_def.h:53
DRV_ADC_SEQ_DEVICE_MSK_E
The adc sequencer device IDs.
Definition: netx_drv_adc.h:118
#define madc_seq0_madc_seq_m0_trigger_Pos
Definition: netx90_app.h:43319
DRV_CALLBACK_F fnMeasurementCompleteCallback[DRV_ADC_MEASUREMENTS_MAX]
Definition: netx_drv_adc.h:489
#define madc_seq1_madc_seq_result_last_mnr_Msk
Definition: netx90_app.h:43769
DRV_STATUS_E DRV_ADC_Seq_Reset(DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
Reset the given adc sequencer.
Definition: netx_drv_adc.c:752
DRV_ADC_STATIC_CFG_T tStaticCfg01
Definition: netx_drv_adc.h:539
__IOM uint32_t madc_seq_tracking_time_mux3
Definition: netx90_app.h:17469
#define madc_seq1_madc_seq_result_current_mnr_Pos
Definition: netx90_app.h:43757
__IOM uint32_t madc_seq_cmd
Definition: netx90_app.h:17698
struct madc_seq0_Type::@4253::@4296 madc_seq_m2_b
struct madc_seq0_Type::@4255::@4297 madc_seq_m3_b
#define madc_seq0_madc_seq_m4_adr_offset_Msk
Definition: netx90_app.h:43358
#define madc_seq0_madc_seq_m7_adr_offset_Msk
Definition: netx90_app.h:43391
__IOM uint32_t madc_seq_m2
Definition: netx90_app.h:17614
DRV_ADC_SEQ_DEVICE_T * ptDevice
Definition: netx_drv_adc.h:521
DRV_ADC_SEQ_MEAS_ADR_OFFSET_E eAdrOffset
Definition: netx_drv_adc.h:437
The handle of the ADC driver.
Definition: netx_drv_adc.h:519
__STATIC_INLINE void DRV_ACD_IRQ_Inline_Handler(DRV_ADC_SEQ_DEVICE_ID_E const eDeviceID)
void DRV_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
This method clears the pending state of a given interrupt.
#define madc_seq1_madc_seq_result_last_mnr_Pos
Definition: netx90_app.h:43768
#define madc_seq0_madc_seq_m0_mux_Pos
Definition: netx90_app.h:43315
__IOM uint32_t madc_seq_m7
Definition: netx90_app.h:17684
DRV_STATUS_E DRV_ADC_Driver_Init(DRV_ADC_HANDLE_T *const ptDriver)
Initializes the adc device and handle by the given configuration.
Definition: netx_drv_adc.c:88
#define DRV_ACD_IRQHandler_Generator(id, _)
#define madc_seq0_madc_seq_result_last_val_Msk
Definition: netx90_app.h:43437
#define madc_seq0_madc_seq_m0_mux_Msk
Definition: netx90_app.h:43316
DRV_ADC_SEQ_MEAS_TRIGGER_E
Trigger condition for measurement.
Definition: netx_drv_adc.h:314
#define madc_seq1_madc_seq_status_m_nr_Pos
Definition: netx90_app.h:43750
volatile uint32_t ulPosition
Definition: netx_drv_adc.h:450
__IOM uint32_t madc_seq_tracking_time_mux6
Definition: netx90_app.h:17499
#define madc_seq0_madc_seq_m3_adr_offset_Msk
Definition: netx90_app.h:43347
#define madc_seq1_madc_seq_result_current_mnr_Msk
Definition: netx90_app.h:43758
__IOM uint32_t madc_seq_tracking_time_mux1
Definition: netx90_app.h:17449
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
#define madc_seq1_madc_seq_status_adc_half_clock_cycle_Msk
Definition: netx90_app.h:43749
DRV_STATUS_E DRV_ADC_Seq_SetSampleSeriesBuffer(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, uint16_t *pulSampleSeries, size_t tSize, DRV_CALLBACK_F fnCallback, void *pUser)
Stores a series of aquired sample of the given adc.
DRV_STATUS_E DRV_ADC_Seq_SetMode(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_CONTINUOUS_MODE_E eMode)
Set mode of the sequencer.
Definition: netx_drv_adc.c:648
struct madc_seq0_Type::@4257::@4298 madc_seq_m4_b
#define DRV_UNLOCK(__HANDLE__)
The release function used.
struct DRV_ADC_SEQ_HANDLE_Ttag DRV_ADC_SEQ_HANDLE_T
Type definition of the adc sequencer handle structure.
Definition: netx_drv_adc.h:496
DRV_ADC_SEQ_MEAS_ENABLE_E eEnable
Definition: netx_drv_adc.h:436
DRV_ADC_SOFT_RESET_E eSoftReset
Definition: netx_drv_adc.h:508
DRV_ADC_CONFIGURATION_T tConfiguration
Definition: netx_drv_adc.h:555
DRV_STATUS_E DRV_ADC_Seq_Stop(DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
Stops the given adc sequencer.
Definition: netx_drv_adc.c:723
#define madc_seq0_madc_seq_m0_trigger_Msk
Definition: netx90_app.h:43320
DRV_STATUS_E DRV_ADC_Seq_Meas_ChangeConfig(DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_MEASUREMENT_E eMeasurement, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E eInputChannel, DRV_ADC_SEQ_MEAS_OVERSAMPLING_E eOversampling, DRV_ADC_SEQ_MEAS_TRIGGER_E eTrigger)
Changes the parameters of the given adc sequencer measurement.
Definition: netx_drv_adc.c:781
DRV_ADC_SEQ_MEAS_TRIGGER_E eTrigger
Definition: netx_drv_adc.h:440
DRV_ADC_SEQ_CLK_PHASE_E eClkPhase
Definition: netx_drv_adc.h:480
#define madc_seq1_madc_seq_result_last_val_Pos
Definition: netx90_app.h:43772
#define madc_seq0_madc_seq_result_last_mnr_Pos
Definition: netx90_app.h:43432
#define madc_seq0_madc_seq_m5_adr_offset_Msk
Definition: netx90_app.h:43369
DRV_ADC_SEQ_DEVICE_ID_E
DRV_OPERATION_MODE_E eOperationMode
Definition: netx_drv_adc.h:475
static DRV_ADC_SEQ_DEVICE_T *const s_apSubDeviceAddressTable[DRV_ADC_SEQ_DEVICE_COUNT]
Table of the sequencer addresses.
Definition: netx_drv_adc.c:62
#define madc_seq0_madc_seq_m0_oversample_Msk
Definition: netx90_app.h:43318
#define madc_seq1_madc_seq_status_adc_half_clock_cycle_Pos
Definition: netx90_app.h:43748
madc_seq0 (madc_seq0)
Definition: netx90_app.h:17397
struct madc_seq0_Type::@4259::@4299 madc_seq_m5_b
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E eInputChannel
Definition: netx_drv_adc.h:438
#define madc_seq0_madc_seq_m2_adr_offset_Msk
Definition: netx90_app.h:43336
DRV_ADC_SEQ_CONTINUOUS_MODE_E eContinuousMode
Definition: netx_drv_adc.h:484