This is the ADC driver, defined by DRV_ADC_HANDLE_T. More...

Collaboration diagram for ADC:

Data Structures
struct	DRV_ADC_SEQ_MEAS_T
	Measurement structure. More...

struct	DRV_ADC_SEQ_BUFFER_T
	Structure for the buffers used for the sequencers data io. More...

struct	DRV_ADC_STATE_T
	Structure containing the state of the adc sequencer. More...

struct	DRV_ADC_SEQ_CONFIGURATION_T
	The configuration of the driver. More...

struct	DRV_ADC_STATIC_CFG_T
	Type definition of the separate ADC configuration structure. More...

struct	DRV_ADC_SEQ_HANDLE_T
	The handle of the ADC driver. More...

struct	DRV_ADC_CONFIGURATION_T
	The configuration of the driver. More...

struct	DRV_ADC_HANDLE_T
	The handle of the driver. More...

Macros
#define	DRV_ADC_CONFIG_DEFAULT
	Default parameter for the initialization of DRV_ADC_CONFIGURATION_T. More...

#define	DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT
	Default parameter for the initialization of DRV_ADC_MEAS_CONFIGURATION_T. More...

#define	DRV_ADC_SEQ_CONFIG_DEFAULT
	Default parameter for the initialization of DRV_ADC_SEQ_CONFIGURATION_T. More...

#define	DRV_ADC_SEQ_CATCHED_NO_RESULT 0xffff
	Result was not accessible after the measurement. More...

#define	DRV_ADC_INITIALIZER (DRV_ADC_HANDLE_T){0, {0, 0, 0, 0}, DRV_ADC_CONFIG_DEFAULT, DRV_LOCK_INITIALIZER_VALUE}
	Default settings for adc device driver. More...

#define	DRV_ADC_SEQ_INITIALIZER (DRV_ADC_SEQ_HANDLE_T){0, 0, DRV_ADC_SEQ_CONFIG_DEFAULT, DRV_LOCK_INITIALIZER_VALUE, {0, 0, 0, 0, 0, 0}}
	Default settings for adc sequencer. More...

#define	DRV_ACD_IRQHandler_Generator(id, _) DRV_Default_IRQHandler_Function_Generator(MADC ## id ## _IRQHandler ,DRV_ACD_IRQ_Inline_Handler,DRV_ADC_SEQ_DEVICE_ID_ADC ## id)

Typedefs
typedef struct DRV_ADC_SEQ_HANDLE_Ttag	DRV_ADC_SEQ_HANDLE_T
	Type definition of the adc sequencer handle structure. More...

typedef struct DRV_ADC_HANDLE_Ttag	DRV_ADC_HANDLE_T
	Type definition of the adc handle structure. More...

Enumerations
enum	DRV_ADC_SEQ_DEVICE_MSK_E { DRV_ADC_SEQ_DEVICE_MSK_0 = 0x1u, DRV_ADC_SEQ_DEVICE_MSK_1 = 0x2u, DRV_ADC_SEQ_DEVICE_MSK_2 = 0x4u, DRV_ADC_SEQ_DEVICE_MSK_3 = 0x8u, DRV_ADC_SEQ_DEVICE_MSK_MIN = DRV_ADC_SEQ_DEVICE_MSK_0, DRV_ADC_SEQ_DEVICE_MSK_MAX = 0xFu }
	The adc sequencer device IDs. More...

enum	DRV_ADC_VREF_BUFFER_E { DRV_ADC_VREF_BUFFER_ENABLED = 0x1u, DRV_ADC_VREF_BUFFER_DISABLED = 0x0u, DRV_ADC_VREF_BUFFER_MIN = DRV_ADC_VREF_BUFFER_DISABLED, DRV_ADC_VREF_BUFFER_MAX = DRV_ADC_VREF_BUFFER_ENABLED }
	Use internal 2.6V reference: More...

enum	DRV_ADC_SEQ_DMA_MODE_E { DRV_ADC_SEQ_DMA_MODE_ENABLED = 0x0u, DRV_ADC_SEQ_DMA_MODE_DISABLED = 0x1u, DRV_ADC_SEQ_DMA_MODE_MIN = DRV_ADC_SEQ_DMA_MODE_ENABLED, DRV_ADC_SEQ_DMA_MODE_MAX = DRV_ADC_SEQ_DMA_MODE_DISABLED }
	Enable or Disable the DMA mode. More...

enum	DRV_ADC_SEQ_32Bit_MODE_E { DRV_ADC_SEQ_32Bit_MODE_ENABLED = 0x1u, DRV_ADC_SEQ_32Bit_MODE_DISABLED = 0x0u, DRV_ADC_SEQ_32Bit_MODE_MIN = DRV_ADC_SEQ_32Bit_MODE_DISABLED, DRV_ADC_SEQ_32Bit_MODE_MAX = DRV_ADC_SEQ_32Bit_MODE_ENABLED }
	The copy engine only uses 32bit addresses and DWord access. This mode wastes memory but speeds up the copy by not running read-modify-write cycles. If deactivated, the default 16bit addresses and Word access is used. More...

enum	DRV_ADC_SEQ_VREF_VDD3_E { DRV_ADC_SEQ_VREF_VDD3_ENABLED = 0x1u, DRV_ADC_SEQ_VREF_VDD3_DISABLED = 0x0u, DRV_ADC_SEQ_VREF_VDD3_MIN = DRV_ADC_SEQ_VREF_VDD3_DISABLED, DRV_ADC_SEQ_VREF_VDD3_MAX = DRV_ADC_SEQ_VREF_VDD3_ENABLED }
	Use core voltage of 3.3V as reference or use Vref of the adc (which can be external or 2.6V). More...

enum	DRV_ADC_SEQ_CLK_SYNC_E { DRV_ADC_SEQ_CLK_SYNC_DISABLED = 0x0u, DRV_ADC_SEQ_CLK_SYNC_ENABLED = 0x1u, DRV_ADC_SEQ_CLK_SYNC_MIN = DRV_ADC_SEQ_CLK_SYNC_DISABLED, DRV_ADC_SEQ_CLK_SYNC_MAX = DRV_ADC_SEQ_CLK_SYNC_ENABLED }
	Synchronization of the adc clocks. More...

enum	DRV_ADC_SEQ_CLK_PHASE_E { DRV_ADC_SEQ_CLK_PHASE_DEFAULT = 0xFFu, DRV_ADC_SEQ_CLK_PHASE_MIN = 0x00u, DRV_ADC_SEQ_CLK_PHASE_MAX = 0xFFu }
	Generation of the rising edge of the adcclk is delayed until the global clk_phase counter matches this value. NOTE: The rising edge of the adcclk ending the first sample period of a triggered measurement is NEVER delayed. More...

enum	DRV_ADC_SEQ_CLK_PERIOD_E { DRV_ADC_SEQ_CLK_PERIOD_DEFAULT = 0x2u, DRV_ADC_SEQ_CLK_PERIOD_MIN = 0x00u, DRV_ADC_SEQ_CLK_PERIOD_MAX = 0xFFu }
	Duration of an adcclk period in system clock cycles-1. More...

enum	DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_E { DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT = 0x4u, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_MIN = 0x00u, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_MAX = 0xFFu }
	ADC sample extension for input channel 0. More...

enum	DRV_ADC_SEQ_MEASUREMENT_E { DRV_ADC_SEQ_MEASUREMENT_0 = 0u, DRV_ADC_SEQ_MEASUREMENT_1 = 1u, DRV_ADC_SEQ_MEASUREMENT_2 = 2u, DRV_ADC_SEQ_MEASUREMENT_3 = 3u, DRV_ADC_SEQ_MEASUREMENT_4 = 4u, DRV_ADC_SEQ_MEASUREMENT_5 = 5u, DRV_ADC_SEQ_MEASUREMENT_6 = 6u, DRV_ADC_SEQ_MEASUREMENT_7 = 7u, DRV_ADC_SEQ_MEASUREMENT_MIN = DRV_ADC_SEQ_MEASUREMENT_0, DRV_ADC_SEQ_MEASUREMENT_MAX = DRV_ADC_SEQ_MEASUREMENT_7 }
	Measurements of the sequencer. More...

enum	DRV_ADC_SEQ_MEAS_ENABLE_E { DRV_ADC_SEQ_MEAS_DISABLE = 0x0u, DRV_ADC_SEQ_MEAS_ENABLE = 0x1u, DRV_ADC_SEQ_MEAS_ENABLE_MIN = DRV_ADC_SEQ_MEAS_DISABLE, DRV_ADC_SEQ_MEAS_ENABLE_MAX = DRV_ADC_SEQ_MEAS_ENABLE }
	Enable measurement configuration. More...

enum	DRV_ADC_SEQ_MEAS_ADR_OFFSET_E { DRV_ADC_SEQ_BASE_ADR_OFFSET_NONE = 0x00u, DRV_ADC_SEQ_BASE_ADR_OFFSET_MIN = DRV_ADC_SEQ_BASE_ADR_OFFSET_NONE, DRV_ADC_SEQ_BASE_ADR_OFFSET_MAX = 0x1Fu }
	Address offset specified in 16 bit words where the sum will be stored. More...

enum	DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E { DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_0 = 0x0u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_1 = 0x1u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_2 = 0x2u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_3 = 0x3u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_4 = 0x4u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_5 = 0x5u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_6 = 0x6u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_7 = 0x7u, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MIN = DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_0, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MAX = DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_7 }
	Input channel multiplexer setting. More...

enum	DRV_ADC_SEQ_MEAS_OVERSAMPLING_E { DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_1 = 0x0ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_2 = 0x1ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_3 = 0x2ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_4 = 0x3ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_5 = 0x4ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_6 = 0x5ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_7 = 0x6ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_8 = 0x7ul, DRV_ADC_SEQ_MEAS_OVERSAMPLING_MIN = DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_1, DRV_ADC_SEQ_MEAS_OVERSAMPLING_MAX = DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_8 }
	Number of samples minus one to sum for this measurement i.e. 0:sum 1 samples, 1:sum 2 samples, ... More...

enum	DRV_ADC_SEQ_MEAS_TRIGGER_E { DRV_ADC_SEQ_MEAS_TRIGGER_CONDITION_MIN = 0x0ul, DRV_ADC_SEQ_MEAS_TRIGGER_CONDITION_MAX = 0x0FFFFul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_0 = 0x10000ul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_1 = 0x10001ul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_2 = 0x10002ul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_3 = 0x10003ul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_4 = 0x10004ul, DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_5 = 0x10005ul, DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_0 = 0x10006ul, DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_1 = 0x10007ul, DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_2 = 0x10008ul, DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_TRIGGER_0 = 0x10009ul, DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_TRIGGER_0 = 0x1000aul, DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_TRIGGER_1 = 0x1000bul, DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_TRIGGER_1 = 0x1000cul, DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_SAMPLE_0 = 0x1000dul, DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_SAMPLE_0 = 0x1000eul, DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_SAMPLE_1 = 0x1000ful, DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_SAMPLE_1 = 0x10010ul, DRV_ADC_SEQ_MEAS_TRIGGER_RESERVED_MIN = 0x10011ul, DRV_ADC_SEQ_MEAS_TRIGGER_RESERVED_MAX = 0x1FFFEul, DRV_ADC_SEQ_MEAS_TRIGGER_IMMEDIATELY = 0x1FFFFul, DRV_ADC_SEQ_MEAS_TRIGGER_MIN = DRV_ADC_SEQ_MEAS_TRIGGER_CONDITION_MIN, DRV_ADC_SEQ_MEAS_TRIGGER_MAX = DRV_ADC_SEQ_MEAS_TRIGGER_IMMEDIATELY }
	Trigger condition for measurement. More...

enum	DRV_ADC_SEQ_CONTINUOUS_MODE_E { DRV_ADC_SEQ_CONTINUOUS_MODE_DISABLED = 0x0ul, DRV_ADC_SEQ_CONTINUOUS_MODE_ENABLED = 0x1ul, DRV_ADC_SEQ_CONTINUOUS_MODE_MIN = DRV_ADC_SEQ_CONTINUOUS_MODE_DISABLED, DRV_ADC_SEQ_CONTINUOUS_MODE_MAX = DRV_ADC_SEQ_CONTINUOUS_MODE_ENABLED }
	Continuous or Single Shot mode of the device and api. More...

enum	DRV_ADC_SEQ_BASE_ADDRESS_E { DRV_ADC_SEQ_BASE_ADDRESS_MIN = 0x00000000u, DRV_ADC_SEQ_BASE_ADDRESS_MAX = 0xFFFFFFFFu }
	Base address for writing the measurement results. More...

enum	DRV_ADC_CLK_PERIOD_E { DRV_ADC_CLK_PERIOD_DEFAULT = 2u, DRV_ADC_CLK_PERIOD_MIN = 0u, DRV_ADC_CLK_PERIOD_MAX = 0xffu }
	Max value of global ADC synchronization counter: More...

enum	DRV_ADC_STATE_MEASUREMENT_E { DRV_ADC_STATE_MEASUREMENT_0 = 0u, DRV_ADC_STATE_MEASUREMENT_1 = 1u, DRV_ADC_STATE_MEASUREMENT_2 = 2u, DRV_ADC_STATE_MEASUREMENT_3 = 3u, DRV_ADC_STATE_MEASUREMENT_4 = 4u, DRV_ADC_STATE_MEASUREMENT_5 = 5u, DRV_ADC_STATE_MEASUREMENT_6 = 6u, DRV_ADC_STATE_MEASUREMENT_7 = 7u, DRV_ADC_STATE_MEASUREMENT_IDLE = 8u, DRV_ADC_STATE_MEASUREMENT_MAX = DRV_ADC_STATE_MEASUREMENT_IDLE }
	The enumeration for the available measurements. More...

enum	DRV_ADC_SOFT_RESET_E { DRV_ADC_SOFT_RESET_ACTIVE = 0u, DRV_ADC_SOFT_RESET_INACTIVE = 1u, DRV_ADC_SOFT_RESET_MIN = DRV_ADC_SOFT_RESET_ACTIVE, DRV_ADC_SOFT_RESET_MAX = DRV_ADC_SOFT_RESET_INACTIVE }
	Soft-Reset configuration of the ADCs. More...

enum	DRV_ADC_POWER_DOWN_E { DRV_ADC_DISABLE = 0u, DRV_ADC_ENABLE = 1u, DRV_ADC_POWER_DOWN_MIN = DRV_ADC_DISABLE, DRV_ADC_POWER_DOWN_MAX = DRV_ADC_ENABLE }
	Power-down mode configuration of the ADCs. More...

enum	DRV_ADC_DEADTIME_E { DRV_ADC_DEADTIME_DEFAULT = 0x000au, DRV_ADC_DEADTIME_MIN = 0x0000u, DRV_ADC_DEADTIME_MAX = 0xffffu }
	Dead time delay configuration of the ADCs. More...

Functions
DRV_STATUS_E	DRV_ADC_HANDLE_T::DRV_ADC_Driver_Init (DRV_ADC_HANDLE_T *const ptDriver)
	Initializes the adc device and handle by the given configuration. More...

DRV_STATUS_E	DRV_ADC_HANDLE_T::DRV_ADC_Driver_DeInit (DRV_ADC_HANDLE_T *const ptDriver)
	Deinitializes the adc device and handle. More...

DRV_STATUS_E	DRV_ADC_HANDLE_T::DRV_ADC_Start (DRV_ADC_HANDLE_T *const ptDriver, DRV_ADC_SEQ_DEVICE_MSK_E eSequencerMask)
	Starts the sequencers given by the mask (software trigger). More...

DRV_STATUS_E	DRV_ADC_HANDLE_T::DRV_ADC_Stop (DRV_ADC_HANDLE_T *const ptDriver, DRV_ADC_SEQ_DEVICE_MSK_E eSequencerMask)
	Stops the sequencers given by the mask. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_Init (DRV_ADC_SEQ_HANDLE_T const ptSequencer, DRV_ADC_HANDLE_T const ptDriver)
	Initializes the adc sequencer and its handle by the given configuration. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_DeInit (DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
	Deinitializes the adc sequencer and its handle. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_SetMode (DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_CONTINUOUS_MODE_E eMode)
	Set mode of the sequencer. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_Start (DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
	Starts the given adc sequencer. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_Stop (DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
	Stops the given adc sequencer. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_Reset (DRV_ADC_SEQ_HANDLE_T *const ptSequencer)
	Reset the given adc sequencer. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_Meas_ChangeConfig (DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_MEASUREMENT_E eMeasurement, DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E eInputChannel, DRV_ADC_SEQ_MEAS_OVERSAMPLING_E eOversampling, DRV_ADC_SEQ_MEAS_TRIGGER_E eTrigger)
	Changes the parameters of the given adc sequencer measurement. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_GetState (DRV_ADC_SEQ_HANDLE_T const ptSequencer, DRV_ADC_STATE_T const ptState)
	Aquires the state of the given adc sequencer. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_GetSample (DRV_ADC_SEQ_HANDLE_T const ptSequencer, uint32_t const pulSample, uint8_t *const pbMeasNr)
	Stores the current acquired sample of the the given adc. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_GetLastSample (DRV_ADC_SEQ_HANDLE_T const ptSequencer, uint32_t const pulSample, uint8_t *const pbMeasNr)
	Stores the last sample of the the given adc. More...

DRV_STATUS_E	DRV_ADC_SEQ_HANDLE_T::DRV_ADC_Seq_SetSampleSeriesBuffer (DRV_ADC_SEQ_HANDLE_T const ptSequencer, uint16_t pulSampleSeries, size_t tSize, DRV_CALLBACK_F fnCallback, void *pUser)
	Stores a series of aquired sample of the given adc. More...

__STATIC_INLINE void	DRV_ADC_SEQ_HANDLE_T::DRV_ACD_IRQ_SaveResult (DRV_ADC_SEQ_HANDLE_T *const ptSequencer, DRV_ADC_SEQ_MEASUREMENT_E const eMeasurement)

__STATIC_INLINE void	DRV_ADC_SEQ_HANDLE_T::DRV_ACD_IRQ_Inline_Handler (DRV_ADC_SEQ_DEVICE_ID_E const eDeviceID)

Variables
static DRV_ADC_DEVICE_T *const	s_apDeviceAddressTable [DRV_ADC_DEVICE_COUNT] = DRV_ADC_DEVICE_LIST
	Table of the device addresses. More...

static DRV_ADC_SEQ_DEVICE_T *const	s_apSubDeviceAddressTable [DRV_ADC_SEQ_DEVICE_COUNT] = DRV_ADC_SEQ_DEVICE_LIST
	Table of the sequencer addresses. More...

static IRQn_Type const	s_apHandleIRQnTable [DRV_ADC_SEQ_DEVICE_COUNT] = DRV_ADC_SEQ_DEVICE_IRQ_LIST
	Table of the IRQ vector numbers. More...

static DRV_ADC_SEQ_HANDLE_T *	s_apHandleAddressTable [DRV_ADC_SEQ_DEVICE_COUNT] = { 0 }
	Used for mapping the handle to an interrupt. More...

Detailed Description

This is the ADC driver, defined by DRV_ADC_HANDLE_T.

The ADC driver is used to interact with the ADC hardware component. The driver is a set of convenience functions to interact with the devices registers.

There are severeal applications of the adc that come to mind.

Get now a single value.
Get continuous sampling to automate the sampling process.
Get a set of samples one after another.
Get a set of samples at the same time.
and more

As every other driver component of the package a context object has to be created first. This objects configuration has to be modified for the task ahead and then the device will be initialized by calling the initialize function on the context.

Macro Definition Documentation

#define DRV_ACD_IRQHandler_Generator	(	id,
		_
	)	DRV_Default_IRQHandler_Function_Generator(MADC ## id ## _IRQHandler ,DRV_ACD_IRQ_Inline_Handler,DRV_ADC_SEQ_DEVICE_ID_ADC ## id)

Definition at line 1152 of file netx_drv_adc.c.

#define DRV_ADC_CONFIG_DEFAULT

Value:

{\
  .eAdcClckPeriod                     = DRV_ADC_CLK_PERIOD_DEFAULT,\
  .eVrefBufferEnable                  = DRV_ADC_VREF_BUFFER_DISABLED,{\
  .eSoftReset                         = DRV_ADC_SOFT_RESET_INACTIVE,\
  .ePowerDown                         = DRV_ADC_ENABLE},{\
  .eSoftReset                         = DRV_ADC_SOFT_RESET_INACTIVE,\
  .ePowerDown                         = DRV_ADC_ENABLE},\
  .auDeadTimeDelay                    = {0, 0, 0, 0, 0, 0}}

Default parameter for the initialization of DRV_ADC_CONFIGURATION_T.

Definition at line 45 of file netx_drv_adc.h.

#define DRV_ADC_INITIALIZER (DRV_ADC_HANDLE_T){0, {0, 0, 0, 0}, DRV_ADC_CONFIG_DEFAULT, DRV_LOCK_INITIALIZER_VALUE}

Default settings for adc device driver.

Use this define for initialize the adc driver structure with default values.

Definition at line 104 of file netx_drv_adc.h.

#define DRV_ADC_SEQ_CATCHED_NO_RESULT 0xffff

Result was not accessible after the measurement.

Possible reason is that the next measurement has already over written the result, before the callback or the irq had the chance to save it.

Definition at line 97 of file netx_drv_adc.h.

#define DRV_ADC_SEQ_CONFIG_DEFAULT

Value:

{\
  .eDeviceID                          = (DRV_ADC_SEQ_DEVICE_ID_E)0,\
  .eOperationMode                     = DRV_OPERATION_MODE_POLL,\
  .eDmaModeDisable                    = DRV_ADC_SEQ_DMA_MODE_DISABLED,\
  .e32BitMode                         = DRV_ADC_SEQ_32Bit_MODE_DISABLED,\
  .eVrefVdd3                          = DRV_ADC_SEQ_VREF_VDD3_DISABLED,\
  .eClkSync                           = DRV_ADC_SEQ_CLK_SYNC_DISABLED,\
  .eClkPhase                          = DRV_ADC_SEQ_CLK_PHASE_DEFAULT,\
  .eClkPeriod                         = DRV_ADC_SEQ_CLK_PERIOD_DEFAULT,\
  .eChannelTrackingTime               = {DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT,\
                                         DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT,\
                                         DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT,\
                                         DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT, DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT},\
  .eContinuousMode                    = DRV_ADC_SEQ_CONTINUOUS_MODE_DISABLED,\
  .eBaseAdr                           = DRV_ADC_SEQ_BASE_ADDRESS_MIN,\
  .tMeasurement                       = {DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT, DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT,\
                                         DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT, DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT,\
                                         DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT, DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT,\
                                         DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT, DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT},\
  .fnSequenceCompleteCallback         = 0,\
  .pSequenceCompleteCallbackHandle    = 0,\
  .fnMeasurementCompleteCallback      = {0, 0, 0, 0, 0, 0, 0, 0},\
  .pMeasurementCompleteCallbackHandle = {0, 0, 0, 0, 0, 0, 0, 0}}

Default parameter for the initialization of DRV_ADC_SEQ_CONFIGURATION_T.

Definition at line 67 of file netx_drv_adc.h.

#define DRV_ADC_SEQ_INITIALIZER (DRV_ADC_SEQ_HANDLE_T){0, 0, DRV_ADC_SEQ_CONFIG_DEFAULT, DRV_LOCK_INITIALIZER_VALUE, {0, 0, 0, 0, 0, 0}}

Default settings for adc sequencer.

Use this define for initialize the adc sequencer structure with default values.

Definition at line 111 of file netx_drv_adc.h.

#define DRV_ADC_SEQ_MEAS_CONFIG_DEFAULT

Value:

{\
  .eEnable                            = DRV_ADC_SEQ_MEAS_DISABLE,\
  .eAdrOffset                         = DRV_ADC_SEQ_BASE_ADR_OFFSET_NONE,\
  .eInputChannel                      = DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_0,\
  .eOversample                        = DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_1,\
  .eTrigger                           = DRV_ADC_SEQ_MEAS_TRIGGER_IMMEDIATELY}

Default parameter for the initialization of DRV_ADC_MEAS_CONFIGURATION_T.

Definition at line 57 of file netx_drv_adc.h.

Typedef Documentation

typedef struct DRV_ADC_HANDLE_Ttag DRV_ADC_HANDLE_T

Type definition of the adc handle structure.

Definition at line 501 of file netx_drv_adc.h.

typedef struct DRV_ADC_SEQ_HANDLE_Ttag DRV_ADC_SEQ_HANDLE_T

Type definition of the adc sequencer handle structure.

Definition at line 496 of file netx_drv_adc.h.

Enumeration Type Documentation

enum DRV_ADC_CLK_PERIOD_E

Max value of global ADC synchronization counter:

ADCs running at same adcclk might interfere. Therefore the ADCs should be able to run in different clk-phases. Adcclk generation will be done within the ADC sequencers. This value is used to configure a global counter for clock phase reference. It's value should be the same or an natural numbered multiple of the value configured in ADC sequencers.

Enumerator
DRV_ADC_CLK_PERIOD_DEFAULT	The default value.
DRV_ADC_CLK_PERIOD_MIN	Min value for boundary checks.
DRV_ADC_CLK_PERIOD_MAX	Max value for boundary checks.

Definition at line 372 of file netx_drv_adc.h.

enum DRV_ADC_DEADTIME_E

Dead time delay configuration of the ADCs.

Delay in steps of system clock (10ns) between Dead Time EVenT from PWM module and trigger. In case of 2nd DTEVT within delay time, the second DTEVT will be lost.

Enumerator
DRV_ADC_DEADTIME_DEFAULT	Dead time delay of 100ns (Default).
DRV_ADC_DEADTIME_MIN	Min value for boundary checks.
DRV_ADC_DEADTIME_MAX	Max value for boundary checks.

Definition at line 424 of file netx_drv_adc.h.

enum DRV_ADC_POWER_DOWN_E

Power-down mode configuration of the ADCs.

Enumerator
DRV_ADC_DISABLE	Disable ADC (Power-down) (Default).
DRV_ADC_ENABLE	Enable ADC (Power-up).
DRV_ADC_POWER_DOWN_MIN	Min value for boundary checks.
DRV_ADC_POWER_DOWN_MAX	Max value for boundary checks.

Definition at line 410 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_32Bit_MODE_E

The copy engine only uses 32bit addresses and DWord access. This mode wastes memory but speeds up the copy by not running read-modify-write cycles. If deactivated, the default 16bit addresses and Word access is used.

Enumerator
DRV_ADC_SEQ_32Bit_MODE_ENABLED	Enables the 32bit addressing mode.
DRV_ADC_SEQ_32Bit_MODE_DISABLED	Disable the 32bit addressing mode.(Default)
DRV_ADC_SEQ_32Bit_MODE_MIN	Min value for boundary checks.
DRV_ADC_SEQ_32Bit_MODE_MAX	Max value for boundary checks .

Definition at line 160 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_BASE_ADDRESS_E

Base address for writing the measurement results.

Word (16 bit) aligned address, LSB is ignored. In case of DRV_ADC_SEQ_32Bit_MODE_ENABLED, bit 1 will be ignored.

Enumerator
DRV_ADC_SEQ_BASE_ADDRESS_MIN	Min value for boundary checks.
DRV_ADC_SEQ_BASE_ADDRESS_MAX	Max value for boundary checks.

Definition at line 359 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_E

ADC sample extension for input channel 0.

Length of 2nd adcclk in steps of 10ns system clock(~ delay of 3rd adcclk edge). The capacitor inside ADC needs time to be charged depending on the driving strength of the external signal. For 12 bit precision, this time should be 9*(Rint+Rext)*C, with Rint=1kOhm and C=7.5pF. The total formula for this value is: tt_add = ceil((6,75 x Rext/kOhm) + 6,75) - adcclk_period/10ns - 2 Set tt_add=4 if calculated value is smaller 4. The total ADC cycle time results in: tcycle = 14 * adcclk_period + clock_sync_delay (max 1 adcclk_period) + tt_add * 10ns.

Enumerator
DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_DEFAULT	Default setting of the device.
DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_MIN	Min value for boundary checks.
DRV_ADC_SEQ_CHANNEL_TRACKING_TIME_MAX	Max value for boundary checks.

Definition at line 225 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_CLK_PERIOD_E

Duration of an adcclk period in system clock cycles-1.

Warning: It is not feasible to differ from the default value. The option to change it is for debugging purposes only. For odd values the high phase of adcclk is one system clock cycle longer than the low phase.

Enumerator
DRV_ADC_SEQ_CLK_PERIOD_DEFAULT	Default setting of the device.
DRV_ADC_SEQ_CLK_PERIOD_MIN	Min value for boundary checks.
DRV_ADC_SEQ_CLK_PERIOD_MAX	Max value for boundary checks.

Definition at line 207 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_CLK_PHASE_E

Generation of the rising edge of the adcclk is delayed until the global clk_phase counter matches this value. NOTE: The rising edge of the adcclk ending the first sample period of a triggered measurement is NEVER delayed.

Warning: It is not feasible to differ from the default value. The option to change it is for debugging purposes only.

Enumerator
DRV_ADC_SEQ_CLK_PHASE_DEFAULT	Default setting of the device.
DRV_ADC_SEQ_CLK_PHASE_MIN	Min value for boundary checks.
DRV_ADC_SEQ_CLK_PHASE_MAX	Max value for boundary checks .

Definition at line 195 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_CLK_SYNC_E

Synchronization of the adc clocks.

Enumerator
DRV_ADC_SEQ_CLK_SYNC_DISABLED	The rising edges of adcclk are generated independently of the other ADCs. (Default)
DRV_ADC_SEQ_CLK_SYNC_ENABLED	Use adc_clock_phase for defined clock phases in relation to other ADC sequencers.
DRV_ADC_SEQ_CLK_SYNC_MIN	Min value for boundary checks.
DRV_ADC_SEQ_CLK_SYNC_MAX	Max value for boundary checks.

Definition at line 182 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_CONTINUOUS_MODE_E

Continuous or Single Shot mode of the device and api.

Enumerator
DRV_ADC_SEQ_CONTINUOUS_MODE_DISABLED	Continuous mode is disabled. (Default)
DRV_ADC_SEQ_CONTINUOUS_MODE_ENABLED	Continuous mode is enabled.
DRV_ADC_SEQ_CONTINUOUS_MODE_MIN	Min value for boundary checks.
DRV_ADC_SEQ_CONTINUOUS_MODE_MAX	Max value for boundary checks.

Definition at line 345 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_DEVICE_MSK_E

The adc sequencer device IDs.

They are used to identify the adc sequencer devices in the driver context.

Enumerator
DRV_ADC_SEQ_DEVICE_MSK_0	The ADC drivers internal mask for ADC Sequencer 0.
DRV_ADC_SEQ_DEVICE_MSK_1	The ADC drivers internal mask for ADC Sequencer 1.
DRV_ADC_SEQ_DEVICE_MSK_2	The ADC drivers internal mask for ADC Sequencer 2.
DRV_ADC_SEQ_DEVICE_MSK_3	The ADC drivers internal mask for ADC Sequencer 3.
DRV_ADC_SEQ_DEVICE_MSK_MIN	Min value for boundary checks.
DRV_ADC_SEQ_DEVICE_MSK_MAX	Max value for boundary checks.

Definition at line 118 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_DMA_MODE_E

Enable or Disable the DMA mode.

If DMA mode disabled, results are not written to memory and can only access by the result register.

Enumerator
DRV_ADC_SEQ_DMA_MODE_ENABLED	Enables the DMA mode.(Default)
DRV_ADC_SEQ_DMA_MODE_DISABLED	Disable the DMA mode.
DRV_ADC_SEQ_DMA_MODE_MIN	Min value for boundary checks.
DRV_ADC_SEQ_DMA_MODE_MAX	Max value for boundary checks .

Definition at line 148 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEAS_ADR_OFFSET_E

Address offset specified in 16 bit words where the sum will be stored.

In case of DRV_ADC_SEQ_32Bit_MODE_ENABLED, this value will be interpreted as 32-bit address.

Enumerator
DRV_ADC_SEQ_BASE_ADR_OFFSET_NONE	None address offset.
DRV_ADC_SEQ_BASE_ADR_OFFSET_MIN	Min value for boundary checks.
DRV_ADC_SEQ_BASE_ADR_OFFSET_MAX	Max value for boundary checks.

Definition at line 267 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEAS_ENABLE_E

Enable measurement configuration.

A measurement sequence consists of up to 8 measurements

Enumerator
DRV_ADC_SEQ_MEAS_DISABLE	Disable measurement. (Default)
DRV_ADC_SEQ_MEAS_ENABLE	Enable measurement.
DRV_ADC_SEQ_MEAS_ENABLE_MIN	Min value for boundary checks.
DRV_ADC_SEQ_MEAS_ENABLE_MAX	Max value for boundary checks.

Definition at line 254 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E

Input channel multiplexer setting.

The input multiplexer will always be set 1 system clock (10ns) before SOF. It will be reset after sampling to ensure a not-connected phase at the one-hot-coded multiplexer switches.

Enumerator
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_0	The input channel 0.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_1	The input channel 1.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_2	The input channel 2.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_3	The input channel 3.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_4	The input channel 4.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_5	The input channel 5.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_6	The input channel 6.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_7	The input channel 7.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MIN	Min value for boundary checks.
DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_MAX	Max value for boundary checks.

Definition at line 280 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEAS_OVERSAMPLING_E

Number of samples minus one to sum for this measurement i.e. 0:sum 1 samples, 1:sum 2 samples, ...

Enumerator
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_1	Sum 1 sample.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_2	Sum 2 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_3	Sum 3 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_4	Sum 4 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_5	Sum 5 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_6	Sum 6 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_7	Sum 7 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_SUM_8	Sum 8 samples.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_MIN	Min value for boundary checks.
DRV_ADC_SEQ_MEAS_OVERSAMPLING_MAX	Max value for boundary checks.

Definition at line 297 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEAS_TRIGGER_E

Trigger condition for measurement.

Enumerator
DRV_ADC_SEQ_MEAS_TRIGGER_CONDITION_MIN	Extended counter (PWM) minimum value.
DRV_ADC_SEQ_MEAS_TRIGGER_CONDITION_MAX	Extended counter (PWM) maximum value.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_0	delayed with dead time delay of PWM channel 0.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_1	delayed with dead time delay of PWM channel 1.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_2	delayed with dead time delay of PWM channel 2.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_3	delayed with dead time delay of PWM channel 3.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_4	delayed with dead time delay of PWM channel 4.
DRV_ADC_SEQ_MEAS_TRIGGER_DELAYED_DTEVT_5	delayed with dead time delay of PWM channel 5.
DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_0	GPIO_APP_COUNTER0 = 0.
DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_1	GPIO_APP_COUNTER1 = 0.
DRV_ADC_SEQ_MEAS_TRIGGER_GPIO_APP_COUNTER_2	GPIO_APP_COUNTER2 = 0.
DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_TRIGGER_0	posedge of xc_trigger[0].
DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_TRIGGER_0	posedge of xc_trigger[1].
DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_TRIGGER_1	negedge of xc_trigger[0].
DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_TRIGGER_1	negedge of xc_trigger[1].
DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_SAMPLE_0	posedge of xc_sample[0].
DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_SAMPLE_0	posedge of xc_sample[1].
DRV_ADC_SEQ_MEAS_TRIGGER_POS_EDGE_XC_SAMPLE_1	negedge of xc_sample[0].
DRV_ADC_SEQ_MEAS_TRIGGER_NEG_EDGE_XC_SAMPLE_1	negedge of xc_sample[1].
DRV_ADC_SEQ_MEAS_TRIGGER_RESERVED_MIN	RESERVED min id.
DRV_ADC_SEQ_MEAS_TRIGGER_RESERVED_MAX	RESERVED max id.
DRV_ADC_SEQ_MEAS_TRIGGER_IMMEDIATELY	no trigger, measurement executes immediately after end of sampling phase.
DRV_ADC_SEQ_MEAS_TRIGGER_MIN	Min value for boundary checks.
DRV_ADC_SEQ_MEAS_TRIGGER_MAX	Max value for boundary checks.

Definition at line 314 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_MEASUREMENT_E

Measurements of the sequencer.

Enumerator
DRV_ADC_SEQ_MEASUREMENT_0	Measurement 0 active.
DRV_ADC_SEQ_MEASUREMENT_1	Measurement 1 active.
DRV_ADC_SEQ_MEASUREMENT_2	Measurement 2 active.
DRV_ADC_SEQ_MEASUREMENT_3	Measurement 3 active.
DRV_ADC_SEQ_MEASUREMENT_4	Measurement 4 active.
DRV_ADC_SEQ_MEASUREMENT_5	Measurement 5 active.
DRV_ADC_SEQ_MEASUREMENT_6	Measurement 6 active.
DRV_ADC_SEQ_MEASUREMENT_7	Measurement 7 active.
DRV_ADC_SEQ_MEASUREMENT_MIN	Min value for boundary checks.
DRV_ADC_SEQ_MEASUREMENT_MAX	Max value for boundary checks.

Definition at line 235 of file netx_drv_adc.h.

enum DRV_ADC_SEQ_VREF_VDD3_E

Use core voltage of 3.3V as reference or use Vref of the adc (which can be external or 2.6V).

Enumerator
DRV_ADC_SEQ_VREF_VDD3_ENABLED	Use reference from pin VDD3 (Analog core supply).
DRV_ADC_SEQ_VREF_VDD3_DISABLED	Use reference from pin VREF_ADC (internally driven C or external reference, s. madc_adc01_static_cfg-vref_buffer_enable).
DRV_ADC_SEQ_VREF_VDD3_MIN	Min value for boundary checks.
DRV_ADC_SEQ_VREF_VDD3_MAX	Max value for boundary checks.

Definition at line 171 of file netx_drv_adc.h.

enum DRV_ADC_SOFT_RESET_E

Soft-Reset configuration of the ADCs.

Enumerator
DRV_ADC_SOFT_RESET_ACTIVE	Soft-Reset is active (Default).
DRV_ADC_SOFT_RESET_INACTIVE	Soft-Reset is inactive.
DRV_ADC_SOFT_RESET_MIN	Min value for boundary checks.
DRV_ADC_SOFT_RESET_MAX	Max value for boundary checks.

Definition at line 399 of file netx_drv_adc.h.

enum DRV_ADC_STATE_MEASUREMENT_E

The enumeration for the available measurements.

Enumerator
DRV_ADC_STATE_MEASUREMENT_0	Measurement 0 active.
DRV_ADC_STATE_MEASUREMENT_1	Measurement 1 active.
DRV_ADC_STATE_MEASUREMENT_2	Measurement 2 active.
DRV_ADC_STATE_MEASUREMENT_3	Measurement 3 active.
DRV_ADC_STATE_MEASUREMENT_4	Measurement 4 active.
DRV_ADC_STATE_MEASUREMENT_5	Measurement 5 active.
DRV_ADC_STATE_MEASUREMENT_6	Measurement 6 active.
DRV_ADC_STATE_MEASUREMENT_7	Measurement 7 active.
DRV_ADC_STATE_MEASUREMENT_IDLE	Measurement idle / not measuring.
DRV_ADC_STATE_MEASUREMENT_MAX	Max value for boundary checks.

Definition at line 382 of file netx_drv_adc.h.

enum DRV_ADC_VREF_BUFFER_E

Use internal 2.6V reference:

This mode requires an external capacitor at pin ADC_VREF, which will be driven to 2.6V from internal vref_buffer. To enable this mode set this bit to 1 and static_cfg-vref=0 inside the related MADC_SEQ module. Use external reference: Use any external reference voltage (<3.3V) at pin ADC_VREF. To enable this mode set this bit to 0 and static_cfg-vref=0 inside the related MADC_SEQ module.

Enumerator
DRV_ADC_VREF_BUFFER_ENABLED	Drive 2.6V on Vref.
DRV_ADC_VREF_BUFFER_DISABLED	Behave passive .
DRV_ADC_VREF_BUFFER_MIN	Min value for boundary checks.
DRV_ADC_VREF_BUFFER_MAX	Max value for boundary checks.

Definition at line 135 of file netx_drv_adc.h.

Function Documentation

__STATIC_INLINE void DRV_ACD_IRQ_Inline_Handler ( DRV_ADC_SEQ_DEVICE_ID_E const eDeviceID )

private

This function is the true interrupt service routine or interrupt handler of the ADC device interrupts. The interrupt handlers called by the controller should inline this handler and the constant eDeviceID should define the specific device in compile time. For debug and development purposes a check of the pointers is performed in front that is not necessary for release. It is necessary because a debugger stopped controller does not perform a reset of the interrupt vector and so the ISR shall cope with the not initialized handle pointer.

Parameters

[in,out] eDeviceID The given id of the drivers class

Returns: void

Definition at line 1111 of file netx_drv_adc.c.

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__STATIC_INLINE void DRV_ACD_IRQ_SaveResult	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		DRV_ADC_SEQ_MEASUREMENT_E const	eMeasurement
	)

private

In-line function for save the result of a single measurement and if necessary, execute the corresponding callback.

Parameters

[in]	ptSequencer	ADC sequencer
[in]	eMeasurement	The number of completed measurement

Returns: void

Definition at line 1049 of file netx_drv_adc.c.

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DRV_STATUS_E DRV_ADC_Driver_DeInit ( DRV_ADC_HANDLE_T *const ptDriver )

Deinitializes the adc device and handle.

Deinitializes the adc driver device and handle.

Parameters

[in] ptDriver Handle of ADC driver

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 154 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Driver_Init ( DRV_ADC_HANDLE_T *const ptDriver )

Initializes the adc device and handle by the given configuration.

The function takes a DRV_SPI_HANDLE_T pointer which contains a DRV_ADC_ATTRIBUTES_T structure.

Parameters

[in] ptDriver Handle of ADC driver

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 88 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_DeInit ( DRV_ADC_SEQ_HANDLE_T *const ptSequencer )

Deinitializes the adc sequencer and its handle.

Deinitializes the adc sequencer device and handle.

Parameters

[in] ptSequencer Handle of ADC sequencer

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 612 of file netx_drv_adc.c.

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DRV_STATUS_E DRV_ADC_Seq_GetLastSample	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		uint32_t *const	pulSample,
		uint8_t *const	pbMeasNr
	)

Stores the last sample of the the given adc.

Get the last acquired sample of the the given adc.

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[out]	pulSample	Value of the last sample
[out]	pbMeasNr	Number of measurement

Returns: DRV_OK DRV_BUSY DRV_ERROR_PARAM

Definition at line 960 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_GetSample	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		uint32_t *const	pulSample,
		uint8_t *const	pbMeasNr
	)

Stores the current acquired sample of the the given adc.

Get the acquired sample of the the given adc. It may be that the retrieved value is not the final result, but only an intermediate value. In this case the return value is DRV_BUSY instead of DRV_OK.

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[out]	pulSample	Value of the current sample
[out]	pbMeasNr	Number of measurement

Returns: DRV_OK DRV_BUSY DRV_ERROR_PARAM

Definition at line 912 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_GetState	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		DRV_ADC_STATE_T *const	ptState
	)

Aquires the state of the given adc sequencer.

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[out]	ptState	State of the ADC sequencer

Returns: DRV_OK DRV_BUSY DRV_ERROR_PARAM

Definition at line 874 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_Init	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		DRV_ADC_HANDLE_T *const	ptDriver
	)

Initializes the adc sequencer and its handle by the given configuration.

Initializes the adc sequencer and its handle by the given configuration..

Parameters

[in]	ptSequencer	Handle of the ADC sequencer
[in]	ptDriver	Handle of ADC driver

Returns: DRV_OK

Definition at line 409 of file netx_drv_adc.c.

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DRV_STATUS_E DRV_ADC_Seq_Meas_ChangeConfig	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		DRV_ADC_SEQ_MEASUREMENT_E	eMeasurement,
		DRV_ADC_SEQ_MEAS_INPUT_CHANNEL_E	eInputChannel,
		DRV_ADC_SEQ_MEAS_OVERSAMPLING_E	eOversampling,
		DRV_ADC_SEQ_MEAS_TRIGGER_E	eTrigger
	)

Changes the parameters of the given adc sequencer measurement.

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[in]	eMeasurement	Measurement
[in]	eInputChannel	Input channel multiplexer setting
[in]	eOversampling	Number of samples minus one to sum for this measurement
[in]	eTrigger	Trigger condition for measurement

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 781 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_Reset ( DRV_ADC_SEQ_HANDLE_T *const ptSequencer )

Reset the given adc sequencer.

Parameters

[in] ptSequencer Handle of ADC sequencer

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 752 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_SetMode	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		DRV_ADC_SEQ_CONTINUOUS_MODE_E	eMode
	)

Set mode of the sequencer.

set mode of the sequencer.

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[in]	eMode	Sequencer mode

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 648 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_SetSampleSeriesBuffer	(	DRV_ADC_SEQ_HANDLE_T *const	ptSequencer,
		uint16_t *	pulSampleSeries,
		size_t	tSize,
		DRV_CALLBACK_F	fnCallback,
		void *	pUser
	)

Stores a series of aquired sample of the given adc.

Set a buffer memory to record a series of samples This function do automatically enable the buffer and after next start of the sequencer, every recored sample will stored continuously into the buffer area. The buffer works like a ring buffer. After every round of filling the buffer, it is possible to execute a callback. Reseting the sequencer will deactivate the buffer. The buffer only works together with the interrupt mode. The buffer memory is word based. (2bytes need for every sample)

Parameters

[in]	ptSequencer	Handle of ADC sequencer
[out]	pulSampleSeries	Pointer to the sample buffer
[in]	tSize	Size of buffer in byte
[in]	fnCallback	the users callback function
[in]	pUser	pointer to user resources to pass through

Returns: DRV_OK DRV_ERROR_PARAM DRV_NSUPP

Definition at line 1015 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_Start ( DRV_ADC_SEQ_HANDLE_T *const ptSequencer )

Starts the given adc sequencer.

Parameters

[in] ptSequencer Handle of ADC sequencer

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 678 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Seq_Stop ( DRV_ADC_SEQ_HANDLE_T *const ptSequencer )

Stops the given adc sequencer.

Parameters

[in] ptSequencer Handle of ADC sequencer

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 723 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Start	(	DRV_ADC_HANDLE_T *const	ptDriver,
		DRV_ADC_SEQ_DEVICE_MSK_E	eSequencerMask
	)

Starts the sequencers given by the mask (software trigger).

Starts the sequencers given by the mask (software trigger). Not configured sequencers will be ignored.

Parameters

[in]	ptDriver	Handle of ADC driver
[in]	eSequencerMask	Mask of sequencers to start

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 183 of file netx_drv_adc.c.

DRV_STATUS_E DRV_ADC_Stop	(	DRV_ADC_HANDLE_T *const	ptDriver,
		DRV_ADC_SEQ_DEVICE_MSK_E	eSequencerMask
	)

Stops the sequencers given by the mask.

Parameters

[in]	ptDriver	Handle of ADC driver
[in]	eSequencerMask	Mask of sequencers to stop

Returns: DRV_OK DRV_ERROR_PARAM

Definition at line 338 of file netx_drv_adc.c.

Variable Documentation

DRV_ADC_DEVICE_T* const s_apDeviceAddressTable[DRV_ADC_DEVICE_COUNT] = DRV_ADC_DEVICE_LIST

static

Table of the device addresses.

Used to identify the device addresses by the device id.

Definition at line 55 of file netx_drv_adc.c.

DRV_ADC_SEQ_HANDLE_T* s_apHandleAddressTable[DRV_ADC_SEQ_DEVICE_COUNT] = { 0 }

static

Used for mapping the handle to an interrupt.

Threadsafe and reentrant because its is only written in normal context an used in interrupt context of the specific interrupt.

Definition at line 76 of file netx_drv_adc.c.

IRQn_Type const s_apHandleIRQnTable[DRV_ADC_SEQ_DEVICE_COUNT] = DRV_ADC_SEQ_DEVICE_IRQ_LIST

static

Table of the IRQ vector numbers.

Used to identify the interrupt channels by the device id.

Definition at line 69 of file netx_drv_adc.c.

DRV_ADC_SEQ_DEVICE_T* const s_apSubDeviceAddressTable[DRV_ADC_SEQ_DEVICE_COUNT] = DRV_ADC_SEQ_DEVICE_LIST

static

Table of the sequencer addresses.

Used to identify the sequencer addresses by the sequencer id.

Definition at line 62 of file netx_drv_adc.c.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation