Hilscher netX microcontroller driver  V0.0.5.0
Documentation of the netX driver package
netx_drv_spi.c
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1 /*!************************************************************************/
20 #include "netx_drv.h"
21 #ifdef DRV_SPI_MODULE_ENABLED
22 
69 static DRV_SPI_DEVICE_U const s_apDeviceAddressTable[DRV_SPI_DEVICE_COUNT] = DRV_SPI_DEVICE_LIST;
70 
74 static DRV_DMAC_PERIPHERAL_E const s_apDeviceDmacTable[DRV_SPI_DEVICE_COUNT] = DRV_SPI_DEVICE_DMA_LIST;
80 static IRQn_Type const s_apHandleIRQnTable[DRV_SPI_DEVICE_COUNT] = DRV_SPI_DEVICE_IRQ_LIST;
86 static DRV_SPI_HANDLE_T * s_apHandleAddressTable[DRV_SPI_DEVICE_COUNT] = { 0 };
87 
91 #ifndef DRV_HANDLE_CHECK_INACTIVE
92 #define DRV_HANDLE_CHECK(handle);\
93  if((handle)==0){ \
94  return DRV_ERROR_PARAM; \
95  }\
96  if((handle)->ptDevice.ptSPI==0){ \
97  return DRV_ERROR_PARAM; \
98  }
99 #else
100 #define DRV_HANDLE_CHECK(handle);
101 #endif
102 
107 static void DRV_SPI_Flush_DMA_Callback_Rx(void * ptDriverHandle, DRV_SPI_HANDLE_T * const ptDriver)
108 {
109  if(ptDriver->TxBufferSize == 0)
110  {
111  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
112  {
113  // After Rx last byte, the bus should be idle in SPI.
114  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
115  }
116  if(ptDriver->tConfiguration.fnCompleteCallback != 0)
117  {
118  ptDriver->tConfiguration.fnCompleteCallback(ptDriver, ptDriver->tConfiguration.pCompleteCallbackHandle);
119  }
120  }
121  ptDriver->RxBuffer = 0;
122  ptDriver->RxBufferSize = 0;
123  ptDriver->RxBufferCounter = 0;
124 }
125 
130 static void DRV_SPI_Flush_DMA_Callback_Tx(void * ptDriverHandle, DRV_SPI_HANDLE_T * const ptDriver)
131 {
132  if(ptDriver->RxBufferSize == 0)
133  {
134  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
135  {
136  // Should not happen, because last byte Rx should still be pending in SPI.
137  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
138  }
139  if(ptDriver->tConfiguration.fnCompleteCallback != 0)
140  {
141  ptDriver->tConfiguration.fnCompleteCallback(ptDriver, ptDriver->tConfiguration.pCompleteCallbackHandle);
142  }
143  }
144  ptDriver->TxBuffer = 0;
145  ptDriver->TxBufferSize = 0;
146  ptDriver->TxBufferCounter = 0;
147 }
148 
167 DRV_STATUS_E DRV_SPI_Init(DRV_SPI_HANDLE_T * const ptDriver)
168 {
169  if(ptDriver == 0)
170  {
171  return DRV_ERROR_PARAM;
172  }
173  ptDriver->tLock = DRV_LOCK_INITIALIZER;
174  DRV_LOCK(ptDriver);
175  if(((uint32_t) ptDriver->tConfiguration.eDataSize > (uint32_t) DRV_SPI_DATA_SIZE_SELECT_MAX))
176  {
177  return DRV_ERROR_PARAM;
178  }
179  if((ptDriver->tConfiguration.eDataSize < DRV_SPI_DATA_SIZE_SELECT_MIN && !(ptDriver->tConfiguration.eDataSize == DRV_SPI_DATA_SIZE_SELECT_RESET)))
180  {
181  return DRV_ERROR_PARAM;
182  }
183  if((ptDriver->tConfiguration.eSPIDeviceID > DRV_SPI_DEVICE_ID_MAX))
184  {
185  return DRV_ERROR_PARAM;
186  }
187  if((ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_MIN))
188  {
189  return DRV_ERROR_PARAM;
190  }
191  if((ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_SLAVE && ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER))
192  {
193  return DRV_ERROR_PARAM;
194  }
195  if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_SQI_BORDER && ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_QSPI_BORDER)
196  {
197  if(ptDriver->tConfiguration.eLoopBackMode == DRV_SPI_LOOP_BACK_MODE_ACTIVE)
198  {
199  //For SQI device not available
200  return DRV_NSUPP;
201  }
202  if(ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_SLAVE)
203  {
204  //For SQI device not available
205  return DRV_NSUPP;
206  }
207  if(ptDriver->tConfiguration.uDummyPattern != DRV_SPI_DUMMYPATTERN_FULL && ptDriver->tConfiguration.uDummyPattern != DRV_SPI_DUMMYPATTERN_NULL)
208  {
209  //For SQI device not available
210  return DRV_NSUPP;
211  }
212  if(ptDriver->tConfiguration.eMISO == DRV_SPI_MISO_INACTIVE)
213  {
214  //For SQI device not available
215  return DRV_NSUPP;
216  }
217  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_FULL && !(ptDriver->tConfiguration.eParallelism == DRV_SPI_PARALLELISM_1BIT))
218  {
219  return DRV_NSUPP;
220  }
221  }
222  else
223  {
224  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_HALF)
225  {
226  return DRV_NSUPP;
227  }
228  }
229  if(ptDriver->tConfiguration.eParallelism != DRV_SPI_PARALLELISM_1BIT && ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_HARDWARE)
230  {
231  //For SQI modes (2&4 bits), chip select is never generated automatically.
232  return DRV_NSUPP;
233  }
234  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
235  {
236  if(ptDriver->tConfiguration.ptSequencerTx == 0 || ptDriver->tConfiguration.ptSequencerRx == 0)
237  {
238  return DRV_ERROR_PARAM;
239  }
240  if((ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER))
241  {
242  // Has to be manual or auto.
243  return DRV_NSUPP;
244  }
245  }
246  s_apHandleAddressTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN] = ptDriver;
247  ptDriver->ptDevice = s_apDeviceAddressTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN];
248  if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_MIN && ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_SQI_BORDER)
249  {
250  ptDriver->ptDevice.ptSPI->spi_cr1 = 0x08080000;
251  ptDriver->ptDevice.ptSPI->spi_cr0 = 0x00080007;
252  ptDriver->ptDevice.ptSPI->spi_imsc = 0x00000000;
253  ptDriver->ptDevice.ptSPI->spi_icr = (unsigned) -1;
254  ptDriver->ptDevice.ptSPI->spi_dmacr = 0x00000000;
255  }
256  else if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_SQI_BORDER
257  && ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_QSPI_BORDER)
258  {
259  ptDriver->ptDevice.ptSQI->sqi_cr1 = 0x08080000;
260  ptDriver->ptDevice.ptSQI->sqi_cr0 = 0x00080007;
261  ptDriver->ptDevice.ptSQI->sqi_tcr = 0x1c000000;
262  ptDriver->ptDevice.ptSQI->sqi_irq_mask = 0x00000000;
263  ptDriver->ptDevice.ptSQI->sqi_irq_raw = (unsigned) -1;
264  ptDriver->ptDevice.ptSQI->sqi_irq_clear = (unsigned) -1;
265  ptDriver->ptDevice.ptSQI->sqi_dmacr = 0x00000000;
266  ptDriver->ptDevice.ptSQI->sqi_pio_oe = 0x00000000;
267  ptDriver->ptDevice.ptSQI->sqi_pio_out = 0x0000000e;
268  ptDriver->ptDevice.ptSQI->sqi_sqirom_cfg = 0x02020004;
269  }
270  else if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_QSPI_BORDER && ptDriver->tConfiguration.eSPIDeviceID <= DRV_SPI_DEVICE_ID_MAX)
271  {
272  return DRV_NSUPP; // device yet not available
273  }
274  else
275  {
276  return DRV_ERROR_PARAM; // Shall never be reached because of the guard on top.
277  }
278  // Configure DMA (channel, IRQ, priority and so on)
279  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
280  {
281  ptDriver->ptDevice.ptSPI->spi_dmacr_b.RXDMAE = 1;
282  ptDriver->ptDevice.ptSPI->spi_dmacr_b.TXDMAE = 1;
283  ptDriver->ptDevice.ptSQI->sqi_dmacr_b.rx_dma_en = 1;
284  ptDriver->ptDevice.ptSQI->sqi_dmacr_b.tx_dma_en = 1;
285 
286  DRV_DMAC_TRANSFER_WIDTH_E width = DRV_DMAC_TRANSFER_WIDTH_8b;
287  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
288  {
289  width = DRV_DMAC_TRANSFER_WIDTH_16b;
290  }
291 
292  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eDeviceID = ptDriver->tConfiguration.eDMARx;
293  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.ePeripheralSource =
294  (DRV_DMAC_PERIPHERAL_E) ((uint32_t) s_apDeviceDmacTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]
295  + 0u);
296  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.ePeripheralDest = DRV_DMAC_PERIPHERAL_MEMORY;
297  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eIncrementationSource = DRV_DMAC_INCREMENTATION_INACTIVE;
298  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eIncrementationDest = DRV_DMAC_INCREMENTATION_ACTIVE;
299  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eTransferWidthSource = width;
300  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eTransferWidthDest = width;
301  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.fCallbackComplete = (DRV_CALLBACK_F) DRV_SPI_Flush_DMA_Callback_Rx;
302  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.ptCallbackHandleComplete = ptDriver;
303 
304  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eDeviceID = ptDriver->tConfiguration.eDMATx;
305  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.ePeripheralSource = DRV_DMAC_PERIPHERAL_MEMORY;
306  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.ePeripheralDest =
307  (DRV_DMAC_PERIPHERAL_E) ((uint32_t) s_apDeviceDmacTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]
308  + 1u);
309  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eIncrementationSource = DRV_DMAC_INCREMENTATION_ACTIVE;
310  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eIncrementationDest = DRV_DMAC_INCREMENTATION_INACTIVE;
311  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eTransferWidthSource = width;
312  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eTransferWidthDest = width;
313  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.fCallbackComplete = (DRV_CALLBACK_F) DRV_SPI_Flush_DMA_Callback_Tx;
314  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.ptCallbackHandleComplete = ptDriver;
315 
316  DRV_STATUS_E ret;
317  if(DRV_OK != (ret = DRV_DMAC_Init(ptDriver->tConfiguration.ptSequencerTx)))
318  {
319  return ret;
320  }
321  if(DRV_OK != (ret = DRV_DMAC_Init(ptDriver->tConfiguration.ptSequencerRx)))
322  {
323  return ret;
324  }
325  }
326  ptDriver->TxBuffer = 0;
327  ptDriver->TxBufferSize = 0;
328  ptDriver->TxBufferCounter = 0;
329  ptDriver->RxBuffer = 0;
330  ptDriver->RxBufferSize = 0;
331  ptDriver->RxBufferCounter = 0;
332  if(ptDriver->tConfiguration.ulDriverTimeout == 0)
333  {
334  ptDriver->tConfiguration.ulDriverTimeout = 0xFFFFFFFFul;
335  }
336  ptDriver->ptDevice.ptSQI->sqi_cr0_b.sio_cfg = 01;
337  ptDriver->ptDevice.ptSPI->spi_cr0_b.netx100_comp = 0x0u;
338  ptDriver->ptDevice.ptSPI->spi_cr0_b.slave_sig_early = ptDriver->tConfiguration.eSlaveSigEarly;
339  ptDriver->ptDevice.ptSPI->spi_cr0_b.filter_in = ptDriver->tConfiguration.eFILTER;
340  ptDriver->ptDevice.ptSPI->spi_cr0_b.format = ptDriver->tConfiguration.eFrameFormat;
341  ptDriver->ptDevice.ptSPI->spi_cr0_b.sck_muladd = ptDriver->tConfiguration.eFrequency;
342  ptDriver->ptDevice.ptSPI->spi_cr0_b.SPH = ptDriver->tConfiguration.uMode.structure.eSPH;
343  ptDriver->ptDevice.ptSPI->spi_cr0_b.SPO = ptDriver->tConfiguration.uMode.structure.eSPO;
344  if(ptDriver->tConfiguration.eDataSize == DRV_SPI_DATA_SIZE_SELECT_RESET)
345  {
346  ptDriver->tConfiguration.eDataSize = DRV_SPI_DATA_SIZE_SELECT_DEFAULT;
347  }
348  ptDriver->ptDevice.ptSPI->spi_cr0_b.datasize = ptDriver->tConfiguration.eDataSize;
349 
350  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
351  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
352  if(ptDriver->tConfiguration.eRxFiFoWm == DRV_SPI_FIFO_WM_RESET)
353  {
354  ptDriver->tConfiguration.eRxFiFoWm = DRV_SPI_FIFO_WM_DEFAULT;
355  }
356  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_wm = ptDriver->tConfiguration.eRxFiFoWm - (unsigned int) DRV_SPI_FIFO_WM_MIN;
357  if(ptDriver->tConfiguration.eTxFiFoWm == DRV_SPI_FIFO_WM_RESET)
358  {
359  ptDriver->tConfiguration.eTxFiFoWm = DRV_SPI_FIFO_WM_DEFAULT;
360  }
361  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_wm = ptDriver->tConfiguration.eTxFiFoWm - (unsigned int) DRV_SPI_FIFO_WM_MIN;
362  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER)
363  {
364  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
365  }
366  else if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_HARDWARE)
367  {
368  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
369  }
370  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss_static = ptDriver->tConfiguration.eFSSStatic;
371  ptDriver->ptDevice.ptSPI->spi_cr1_b.SOD = ptDriver->tConfiguration.eMISO;
372  ptDriver->ptDevice.ptSPI->spi_cr1_b.MS = ptDriver->tConfiguration.eBehaviour;
373  ptDriver->ptDevice.ptSPI->spi_cr1_b.SSE = 0x01u;
374  ptDriver->ptDevice.ptSPI->spi_cr1_b.LBM = ptDriver->tConfiguration.eLoopBackMode;
375 
376  // Configure nvic (activate IRQ, define priority and so on)
377  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_IRQ)
378  {
379  DRV_NVIC_ClearPendingIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
380  DRV_NVIC_EnableIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
381  }
382  DRV_UNLOCK(ptDriver);
383  return DRV_OK;
384 }
385 
397 DRV_STATUS_E DRV_SPI_DeInit(DRV_SPI_HANDLE_T * const ptDriver)
398 {
399  DRV_HANDLE_CHECK(ptDriver);
400  DRV_LOCK(ptDriver);
401  DRV_NVIC_DisableIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
402  DRV_NVIC_ClearPendingIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
403  ptDriver->ptDevice.ptSQI->sqi_irq_mask = 0u;
404  ptDriver->ptDevice.ptSQI->sqi_irq_clear = 0xFFFFFFFFul;
405  *ptDriver = (DRV_SPI_HANDLE_T ) { { 0 } };
406  return DRV_OK;
407 }
408 
424 __STATIC_INLINE DRV_STATUS_E DRV_SPI_Flush_Buffers(DRV_SPI_HANDLE_T * const ptDriver)
425 {
426  size_t border;
427  size_t i;
428 // Hardware half or full duplex
429  if(ptDriver->RxBufferCounter != ptDriver->RxBufferSize)
430  {
431  border = ptDriver->ptDevice.ptSPI->spi_sr_b.rx_fifo_level;
432  if(ptDriver->RxBufferCounter + border >= ptDriver->RxBufferSize)
433  {
434  border = ptDriver->RxBufferSize - ptDriver->RxBufferCounter;
435  }
436  for(i = 0; i < border; i++)
437  {
438  // Software half or full duplex
439  if(ptDriver->RxBuffer == 0)
440  {
441  volatile uint32_t tmp = ptDriver->ptDevice.ptSPI->spi_dr;
442  UNUSED(tmp); // UNUSED
443  }
444  else
445  {
446  uint32_t ulTMP = ptDriver->ptDevice.ptSPI->spi_dr;
447  switch (ptDriver->tConfiguration.eParallelism)
448  {
449  case DRV_SPI_PARALLELISM_2BIT:
450  case DRV_SPI_PARALLELISM_4BIT:
451  {
452  ((uint32_t*) ptDriver->RxBuffer)[ptDriver->RxBufferCounter + i] = ulTMP;
453  break;
454  }
455  default:
456  {
457  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
458  {
459  ((uint16_t*) ptDriver->RxBuffer)[ptDriver->RxBufferCounter + i] = ulTMP;
460  }
461  else
462  {
463  ((uint8_t*) ptDriver->RxBuffer)[ptDriver->RxBufferCounter + i] = ulTMP;
464  }
465  break;
466  }
467  }
468  }
469  }
470  ptDriver->RxBufferCounter += border;
471  }
472  // Hardware half or full duplex
473  if(ptDriver->TxBufferCounter != ptDriver->TxBufferSize)
474  {
475  border = 16 - ptDriver->ptDevice.ptSPI->spi_sr_b.tx_fifo_level;
476  if(ptDriver->TxBufferCounter + border >= ptDriver->TxBufferSize)
477  {
478  border = ptDriver->TxBufferSize - ptDriver->TxBufferCounter;
479  }
480  for(i = 0; i < border; i++)
481  {
482  // Software half or full duplex
483  if(ptDriver->TxBuffer == 0)
484  {
485  ptDriver->ptDevice.ptSPI->spi_dr = ptDriver->tConfiguration.uDummyPattern;
486  }
487  else
488  {
489  switch (ptDriver->tConfiguration.eParallelism)
490  {
491  case DRV_SPI_PARALLELISM_2BIT:
492  case DRV_SPI_PARALLELISM_4BIT:
493  {
494  ptDriver->ptDevice.ptSPI->spi_dr = ((uint32_t*) ptDriver->TxBuffer)[ptDriver->TxBufferCounter + i];
495  break;
496  }
497  default:
498  {
499  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
500  {
501  ptDriver->ptDevice.ptSPI->spi_dr = (uint32_t) ((uint16_t*) ptDriver->TxBuffer)[ptDriver->TxBufferCounter + i];
502  }
503  else
504  {
505  ptDriver->ptDevice.ptSPI->spi_dr = (uint32_t) ((uint8_t*) ptDriver->TxBuffer)[ptDriver->TxBufferCounter + i];
506  }
507  break;
508  }
509  }
510  }
511  }
512  ptDriver->TxBufferCounter += border;
513  }
514 
515  return DRV_OK;
516 }
517 
532 static DRV_STATUS_E DRV_SPI_Flush_POLL(DRV_SPI_HANDLE_T * const ptDriver)
533 {
534  ptDriver->ullFrameStartTick = 0;
535  DRV_STATUS_E ret = DRV_OK;
536  while(ptDriver->TxBufferCounter < ptDriver->TxBufferSize || ptDriver->RxBufferCounter < ptDriver->RxBufferSize)
537  {
538  ret = DRV_SPI_Flush_Buffers(ptDriver);
539  if(ptDriver->ullFrameStartTick++ > ptDriver->tConfiguration.ulDriverTimeout)
540  {
541  ret = DRV_TOUT;
542  break;
543  }
544  }
545  while(ptDriver->ptDevice.ptSPI->spi_sr_b.BSY == 1 || ptDriver->ptDevice.ptSPI->spi_sr_b.RNE || !ptDriver->ptDevice.ptSPI->spi_sr_b.TFE)
546  {
547  if(ptDriver->ullFrameStartTick++ > ptDriver->tConfiguration.ulDriverTimeout)
548  {
549  ret = DRV_TOUT;
550  break;
551  }
552  }
553  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
554  {
555  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
556  }
557  if(ptDriver->ullFrameStartTick < ptDriver->tConfiguration.ulDriverTimeout)
558  {
559  if(ptDriver->tConfiguration.fnCompleteCallback != 0)
560  {
561  ptDriver->tConfiguration.fnCompleteCallback(ptDriver, ptDriver->tConfiguration.pCompleteCallbackHandle);
562  }
563  ptDriver->TxBuffer = 0;
564  ptDriver->TxBufferSize = 0;
565  ptDriver->TxBufferCounter = 0;
566  ptDriver->RxBuffer = 0;
567  ptDriver->RxBufferSize = 0;
568  ptDriver->RxBufferCounter = 0;
569  }
570  return ret;
571 }
582 static DRV_STATUS_E DRV_SPI_Flush_IRQ(DRV_SPI_HANDLE_T * const ptDriver)
583 {
584  DRV_STATUS_E ret = DRV_OK;
585  (void) DRV_IRQ_Disable();
586  if((ptDriver->tConfiguration.eRxFiFoWm - 1u) < ptDriver->RxBufferSize - ptDriver->RxBufferCounter)
587  {
588  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_wm = ptDriver->tConfiguration.eRxFiFoWm - 1;
589  }
590  else
591  {
592  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_wm = ptDriver->RxBufferSize - ptDriver->RxBufferCounter - 1;
593  }
594  if(ptDriver->tConfiguration.eTxFiFoWm - 1u < ptDriver->TxBufferSize - ptDriver->TxBufferCounter)
595  {
596  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_wm = ptDriver->tConfiguration.eTxFiFoWm - 1;
597  }
598  else
599  {
600  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_wm = ptDriver->TxBufferSize - ptDriver->TxBufferCounter;
601  }
602  ptDriver->ptDevice.ptSPI->spi_imsc_b.RXIM = 1u; // Mask set and clear RW
603  ptDriver->ptDevice.ptSPI->spi_imsc_b.TXIM = 1u; // Mask set and clear RW
604  ptDriver->ptDevice.ptSPI->spi_imsc_b.RTIM = 1u; // Mask set and clear RW
605  ptDriver->ptDevice.ptSQI->sqi_irq_mask_b.trans_end = 1u;
606  (void) DRV_IRQ_Enable();
607  return ret;
608 }
609 
624 static DRV_STATUS_E DRV_SPI_Flush_DMA(DRV_SPI_HANDLE_T * const ptDriver)
625 {
626  if(ptDriver->RxBufferSize > 0x0FFFu || ptDriver->TxBufferSize > 0x0FFFu)
627  {
628  return DRV_ERROR_PARAM;
629  }
630  if(ptDriver->tConfiguration.ptSequencerTx == 0 || ptDriver->tConfiguration.ptSequencerRx == 0)
631  {
632  return DRV_ERROR_PARAM;
633  }
634  DRV_STATUS_E ret0 = DRV_OK;
635  size_t ulBitCnt;
636  switch (ptDriver->tConfiguration.eParallelism)
637  {
638  case DRV_SPI_PARALLELISM_1BIT:
639  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
640  {
641  ulBitCnt = 2;
642  }
643  else
644  {
645  ulBitCnt = 1;
646  }
647  break;
648  case DRV_SPI_PARALLELISM_2BIT:
649  ulBitCnt = 2;
650  break;
651  case DRV_SPI_PARALLELISM_4BIT:
652  ulBitCnt = 4;
653  break;
654  default:
655  return DRV_ERROR_PARAM;
656  }
657 // Hardware half or full duplex
658  if(ptDriver->RxBufferCounter != ptDriver->RxBufferSize)
659  {
660  // Software half or full duplex
661  if(ptDriver->RxBuffer != 0)
662  {
663  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eIncrementationDest = DRV_DMAC_INCREMENTATION_ACTIVE;
664  ret0 = DRV_DMAC_Start(ptDriver->tConfiguration.ptSequencerRx, (void * const ) &ptDriver->ptDevice.ptSPI->spi_dr, ptDriver->RxBuffer,
665  ptDriver->RxBufferSize * ulBitCnt);
666  }
667  else
668  {
669  ptDriver->tConfiguration.ptSequencerRx->tConfiguration.eIncrementationDest = DRV_DMAC_INCREMENTATION_INACTIVE;
670  ret0 = DRV_DMAC_Start(ptDriver->tConfiguration.ptSequencerRx, (void * const ) &ptDriver->ptDevice.ptSPI->spi_dr,
671  (void * const ) &ptDriver->RxBuffer, ptDriver->RxBufferSize * ulBitCnt);
672  }
673  }
674  DRV_STATUS_E ret1 = DRV_OK;
675 // Hardware half or full duplex
676  if(ptDriver->TxBufferCounter != ptDriver->TxBufferSize)
677  {
678  // Software half or full duplex
679  if(ptDriver->TxBuffer != 0)
680  {
681  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eIncrementationSource = DRV_DMAC_INCREMENTATION_ACTIVE;
682  ret1 = DRV_DMAC_Start(ptDriver->tConfiguration.ptSequencerTx, ptDriver->TxBuffer, (void * const ) &ptDriver->ptDevice.ptSPI->spi_dr,
683  ptDriver->TxBufferSize * ulBitCnt);
684  }
685  else
686  {
687  ptDriver->tConfiguration.ptSequencerTx->tConfiguration.eIncrementationSource = DRV_DMAC_INCREMENTATION_INACTIVE;
688  ret1 = DRV_DMAC_Start(ptDriver->tConfiguration.ptSequencerTx, (void * const ) &ptDriver->tConfiguration.uDummyPattern,
689  (void * const ) &ptDriver->ptDevice.ptSPI->spi_dr, ptDriver->TxBufferSize * ulBitCnt);
690  }
691  }
692  if(ret1 == ret0)
693  {
694  return ret0;
695  }
696  else
697  {
698  return DRV_ERROR;
699  }
700 }
701 
723 DRV_STATUS_E DRV_SPI_Transmit(DRV_SPI_HANDLE_T * const ptDriver, uint8_t* pcData, size_t size)
724 {
725  DRV_HANDLE_CHECK(ptDriver);
726  DRV_LOCK(ptDriver);
727  if(pcData == 0 || size == 0 || size > 0x7ffff)
728  {
729  DRV_UNLOCK(ptDriver);
730  return DRV_ERROR_PARAM;
731  }
732  DRV_STATUS_E ret = DRV_ERROR;
733  if(DRV_OK == (ret = DRV_SPI_GetState(ptDriver, 0)))
734  {
735  size_t ulArraySize = size;
736  switch (ptDriver->tConfiguration.eParallelism)
737  {
738  case DRV_SPI_PARALLELISM_1BIT:
739  {
740  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
741  {
742  ulArraySize += (2 - ulArraySize) % 2;
743  ulArraySize /= 2;
744  }
745  break;
746  }
747  case DRV_SPI_PARALLELISM_2BIT:
748  case DRV_SPI_PARALLELISM_4BIT:
749  {
750  ulArraySize += (4 - ulArraySize) % 4;
751  ulArraySize /= 4;
752  break;
753  }
754  default:
755  {
756  break;
757  }
758  }
759  ptDriver->TxBuffer = pcData;
760  ptDriver->TxBufferSize = ulArraySize;
761  ptDriver->TxBufferCounter = 0;
762  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_FULL)
763  {
764  ptDriver->RxBuffer = 0;
765  ptDriver->RxBufferSize = ulArraySize;
766  ptDriver->RxBufferCounter = 0;
767  }
768  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
769  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
770  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
771  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
772  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
773  {
774  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
775  }
776  if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_SQI_BORDER && ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_QSPI_BORDER)
777  {
778  ptDriver->ptDevice.ptSQI->sqi_cr1_b.spi_trans_ctrl = 1u;
779  ptDriver->ptDevice.ptSQI->sqi_tcr_b.mode = ptDriver->tConfiguration.eParallelism;
780  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_FULL)
781  {
782  ptDriver->ptDevice.ptSQI->sqi_tcr_b.duplex = 3u;
783  }
784  else if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_HALF)
785  {
786  ptDriver->ptDevice.ptSQI->sqi_tcr_b.duplex = 2u;
787  }
788  else
789  {
790  DRV_UNLOCK(ptDriver);
791  return DRV_ERROR;
792  }
793  ptDriver->ptDevice.ptSQI->sqi_tcr_b.transfer_size = size - 1;
794  ptDriver->ptDevice.ptSQI->sqi_tcr_b.start_transfer = 1;
795  }
796  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_POLL)
797  {
798  ret = DRV_SPI_Flush_POLL(ptDriver);
799  }
800  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_IRQ)
801  {
802  ret = DRV_SPI_Flush_IRQ(ptDriver);
803  }
804  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
805  {
806  ret = DRV_SPI_Flush_DMA(ptDriver);
807  }
808  else
809  {
810  ret = DRV_ERROR_PARAM;
811  }
812  }
813  DRV_UNLOCK(ptDriver);
814  return ret;
815 }
816 
840 DRV_STATUS_E DRV_SPI_Receive(DRV_SPI_HANDLE_T * const ptDriver, uint8_t* pcData, size_t size)
841 {
842  DRV_HANDLE_CHECK(ptDriver);
843  DRV_LOCK(ptDriver);
844  if(pcData == 0 || size == 0 || size > 0x7ffff)
845  {
846  DRV_UNLOCK(ptDriver);
847  return DRV_ERROR_PARAM;
848  }
849  DRV_STATUS_E ret = DRV_ERROR;
850  if(DRV_OK == (ret = DRV_SPI_GetState(ptDriver, 0)))
851  {
852  size_t ulArraySize = size;
853  switch (ptDriver->tConfiguration.eParallelism)
854  {
855  case DRV_SPI_PARALLELISM_1BIT:
856  {
857  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
858  {
859  ulArraySize += (2 - ulArraySize) % 2;
860  ulArraySize /= 2;
861  }
862  break;
863  }
864  case DRV_SPI_PARALLELISM_2BIT:
865  case DRV_SPI_PARALLELISM_4BIT:
866  {
867  ulArraySize += (4 - ulArraySize) % 4;
868  ulArraySize /= 4;
869  break;
870  }
871  default:
872  {
873  break;
874  }
875  }
876  ptDriver->RxBuffer = pcData;
877  ptDriver->RxBufferSize = ulArraySize;
878  ptDriver->RxBufferCounter = 0;
879  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_FULL)
880  {
881  ptDriver->TxBuffer = 0;
882  ptDriver->TxBufferSize = ulArraySize;
883  ptDriver->TxBufferCounter = 0;
884  }
885  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
886  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
887  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
888  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
889  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
890  {
891  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
892  }
893  if(ptDriver->tConfiguration.eSPIDeviceID >= DRV_SPI_DEVICE_ID_SQI_BORDER && ptDriver->tConfiguration.eSPIDeviceID < DRV_SPI_DEVICE_ID_QSPI_BORDER)
894  {
895  ptDriver->ptDevice.ptSQI->sqi_cr1_b.spi_trans_ctrl = 1u;
896  ptDriver->ptDevice.ptSQI->sqi_tcr_b.mode = ptDriver->tConfiguration.eParallelism;
897  if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_FULL)
898  {
899  ptDriver->ptDevice.ptSQI->sqi_tcr_b.duplex = 3u;
900  }
901  else if(ptDriver->tConfiguration.eDuplex == DRV_SPI_DUPLEX_HALF)
902  {
903  ptDriver->ptDevice.ptSQI->sqi_tcr_b.duplex = 1u;
904  }
905  else
906  {
907  DRV_UNLOCK(ptDriver);
908  return DRV_ERROR;
909  }
910  ptDriver->ptDevice.ptSQI->sqi_tcr_b.transfer_size = size - 1;
911  ptDriver->ptDevice.ptSQI->sqi_tcr_b.start_transfer = 1;
912  }
913  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_POLL)
914  {
915  ret = DRV_SPI_Flush_POLL(ptDriver);
916  }
917  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_IRQ)
918  {
919  ret = DRV_SPI_Flush_IRQ(ptDriver);
920  }
921  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
922  {
923  ret = DRV_SPI_Flush_DMA(ptDriver);
924  }
925  else
926  {
927  ret = DRV_ERROR_PARAM;
928  }
929  }
930  DRV_UNLOCK(ptDriver);
931  return ret;
932 }
933 
956 DRV_STATUS_E DRV_SPI_TransmitReceive(DRV_SPI_HANDLE_T * const ptDriver, uint8_t* pcTxData, uint8_t* pcRxData, size_t size)
957 {
958  DRV_HANDLE_CHECK(ptDriver);
959  DRV_LOCK(ptDriver);
960  DRV_STATUS_E ret = DRV_OK;
961  if(ptDriver->tConfiguration.eDuplex != DRV_SPI_DUPLEX_FULL)
962  {
963  DRV_UNLOCK(ptDriver);
964  return DRV_NSUPP;
965  }
966  if(pcTxData == 0 || pcRxData == 0 || size == 0 || size > 0x7ffff)
967  {
968  DRV_UNLOCK(ptDriver);
969  return DRV_ERROR_PARAM;
970  }
971  if(DRV_OK == (ret = DRV_SPI_GetState(ptDriver, 0)))
972  {
973  size_t ulArraySize = size;
974  if(ptDriver->tConfiguration.eDataSize > DRV_SPI_DATA_SIZE_SELECT_8b)
975  {
976  ulArraySize += (2 - ulArraySize) % 2;
977  ulArraySize /= 2;
978  }
979  ptDriver->TxBuffer = pcTxData;
980  ptDriver->TxBufferSize = ulArraySize;
981  ptDriver->TxBufferCounter = 0;
982  ptDriver->RxBuffer = pcRxData;
983  ptDriver->RxBufferSize = ulArraySize;
984  ptDriver->RxBufferCounter = 0;
985  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
986  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
987  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 0x01u;
988  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 0x01u;
989  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER && ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
990  {
991  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
992  }
993  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_POLL)
994  {
995  ret = DRV_SPI_Flush_POLL(ptDriver);
996  }
997  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_IRQ)
998  {
999  ret = DRV_SPI_Flush_IRQ(ptDriver);
1000  }
1001  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
1002  {
1003  ret = DRV_SPI_Flush_DMA(ptDriver);
1004  }
1005  else
1006  {
1007  ret = DRV_ERROR_PARAM;
1008  }
1009  }
1010  DRV_UNLOCK(ptDriver);
1011  return ret;
1012 }
1013 
1031 DRV_STATUS_E DRV_SPI_ChangeFss(DRV_SPI_HANDLE_T * const ptDriver, DRV_SPI_FSS_E eFss)
1032 {
1033  DRV_HANDLE_CHECK(ptDriver);
1034  DRV_LOCK(ptDriver);
1035  DRV_STATUS_E ret = DRV_ERROR;
1036  if(DRV_OK == (ret = DRV_SPI_GetState(ptDriver, 0)))
1037  {
1038  ptDriver->tConfiguration.eFSS = eFss;
1039  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER)
1040  {
1041  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
1042  }
1043  else
1044  {
1045  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
1046  }
1047  ret = DRV_OK;
1048  }
1049  DRV_UNLOCK(ptDriver);
1050  return ret;
1051 }
1052 
1068 DRV_STATUS_E DRV_SPI_Abort(DRV_SPI_HANDLE_T * const ptDriver)
1069 {
1070  DRV_HANDLE_CHECK(ptDriver);
1071  DRV_LOCK(ptDriver);
1072  DRV_STATUS_E ret = DRV_ERROR;
1073  if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_POLL)
1074  {
1075  ret = DRV_NSUPP;
1076  }
1077  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_IRQ)
1078  {
1079  ptDriver->ptDevice.ptSPI->spi_cr0_b.sck_muladd = DRV_SPI_FREQUENCY_STOPPED;
1080  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
1081  ptDriver->ptDevice.ptSPI->spi_cr1_b.SSE = 0;
1082  ptDriver->ptDevice.ptSPI->spi_imsc = 0;
1083  ptDriver->ptDevice.ptSPI->spi_icr = 0xFFFFFFFF;
1084  DRV_NVIC_DisableIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
1085  ptDriver->TxBuffer = 0;
1086  ptDriver->TxBufferSize = 0;
1087  ptDriver->TxBufferCounter = 0;
1088  ptDriver->RxBuffer = 0;
1089  ptDriver->RxBufferSize = 0;
1090  ptDriver->RxBufferCounter = 0;
1091  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 1;
1092  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 1;
1093  ptDriver->ptDevice.ptSPI->spi_cr0_b.sck_muladd = ptDriver->tConfiguration.eFrequency;
1094  if(ptDriver->tConfiguration.eFSSStatic != DRV_SPI_FSS_STATIC_DRIVER)
1095  {
1096  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
1097  }
1098  DRV_NVIC_ClearPendingIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
1099  DRV_NVIC_EnableIRQ(s_apHandleIRQnTable[(uint32_t) ptDriver->tConfiguration.eSPIDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN]);
1100  ptDriver->ptDevice.ptSPI->spi_cr1_b.SSE = 1;
1101  ret = DRV_OK;
1102  }
1103  else if(ptDriver->tConfiguration.eOperationMode == DRV_OPERATION_MODE_DMA)
1104  {
1105  ret = DRV_OK;
1106  ptDriver->ptDevice.ptSPI->spi_cr0_b.sck_muladd = DRV_SPI_FREQUENCY_STOPPED;
1107  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
1108  ptDriver->ptDevice.ptSPI->spi_cr1_b.SSE = 0;
1109  ptDriver->ptDevice.ptSPI->spi_imsc = 0;
1110  ptDriver->ptDevice.ptSPI->spi_icr = 0xFFFFFFFF;
1111  if(DRV_DMAC_Abort(ptDriver->tConfiguration.ptSequencerRx) != (ret = DRV_DMAC_Abort(ptDriver->tConfiguration.ptSequencerTx)))
1112  {
1113  ret = DRV_ERROR;
1114  }
1115  ptDriver->TxBuffer = 0;
1116  ptDriver->TxBufferSize = 0;
1117  ptDriver->TxBufferCounter = 0;
1118  ptDriver->RxBuffer = 0;
1119  ptDriver->RxBufferSize = 0;
1120  ptDriver->RxBufferCounter = 0;
1121  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_clr = 1;
1122  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_clr = 1;
1123  ptDriver->ptDevice.ptSPI->spi_cr0_b.sck_muladd = ptDriver->tConfiguration.eFrequency;
1124  if(ptDriver->tConfiguration.eFSSStatic != DRV_SPI_FSS_STATIC_DRIVER)
1125  {
1126  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = ptDriver->tConfiguration.eFSS;
1127  }
1128  ptDriver->ptDevice.ptSPI->spi_cr1_b.SSE = 1;
1129  }
1130  else
1131  {
1132  ret = DRV_ERROR_PARAM;
1133  }
1134  DRV_UNLOCK(ptDriver);
1135  return ret;
1136 }
1137 
1159 DRV_STATUS_E DRV_SPI_GetState(DRV_SPI_HANDLE_T * const ptDriver, DRV_SPI_STATE_E * const ptState)
1160 {
1161  DRV_HANDLE_CHECK(ptDriver);
1162  DRV_STATUS_E ret = DRV_ERROR;
1163  if(ptState != 0)
1164  {
1165  *ptState = (DRV_SPI_STATE_E) ptDriver->ptDevice.ptSPI->spi_sr;
1166  }
1167  if(ptDriver->ptDevice.ptSPI->spi_sr_b.BSY == 1 || ptDriver->TxBuffer != 0 || ptDriver->TxBufferSize != 0 || ptDriver->TxBufferCounter != 0
1168  || ptDriver->RxBuffer != 0 || ptDriver->RxBufferSize != 0 || ptDriver->RxBufferCounter != 0)
1169  {
1170  ret = DRV_BUSY;
1171  }
1172  else
1173  {
1174  ret = DRV_OK;
1175  }
1176  if((ptDriver->ptDevice.ptSPI->spi_sr
1177  & ((uint32_t) DRV_SPI_STATE_RX_FIFO_OVERFLOW | (uint32_t) DRV_SPI_STATE_RX_FIFO_UNDERRUN | (uint32_t) DRV_SPI_STATE_TX_FIFO_OVERFLOW
1178  | (uint32_t) DRV_SPI_STATE_TX_FIFO_UNDERRUN)) != 0)
1179  {
1180  ret = DRV_ERROR_BUFFER;
1181  }
1182  return ret;
1183 }
1184 
1199 __STATIC_INLINE void DRV_SPI_IRQ_Inline_Handler(DRV_SPI_DEVICE_ID_E const eDeviceID)
1200 {
1201  uint32_t ulDeviceOffset = (uint32_t) eDeviceID - (uint32_t) DRV_SPI_DEVICE_ID_MIN;
1202  DRV_SPI_HANDLE_T * const ptDriver = s_apHandleAddressTable[ulDeviceOffset];
1203 #ifndef NDEBUG
1204  if(ptDriver->ptDevice.pt != s_apDeviceAddressTable[ulDeviceOffset].pt)
1205  {
1206  ((DRV_SPI_DEVICE_U const) s_apDeviceAddressTable[ulDeviceOffset]).ptSPI->spi_imsc = 0;
1207  DRV_NVIC_DisableIRQ(s_apHandleIRQnTable[ulDeviceOffset]);
1208  return;
1209  }
1210 #endif
1211  DRV_SPI_Flush_Buffers(ptDriver); //lint !e534
1212  if(ptDriver->RxBufferCounter == ptDriver->RxBufferSize)
1213  {
1214  ptDriver->ptDevice.ptSPI->spi_imsc_b.RXIM = 0; // Mask set and clear RW
1215  }
1216  else
1217  {
1218  if(ptDriver->tConfiguration.eRxFiFoWm - 1u > ptDriver->RxBufferSize - ptDriver->RxBufferCounter)
1219  {
1220  ptDriver->ptDevice.ptSPI->spi_cr1_b.rx_fifo_wm = ptDriver->RxBufferSize - ptDriver->RxBufferCounter - 1;
1221  }
1222  }
1223  if(ptDriver->TxBufferCounter == ptDriver->TxBufferSize)
1224  {
1225  ptDriver->ptDevice.ptSPI->spi_imsc_b.TXIM = 0; // Mask set and clear RW
1226  }
1227  else
1228  {
1229  if(ptDriver->tConfiguration.eTxFiFoWm - 1u > ptDriver->TxBufferSize - ptDriver->TxBufferCounter)
1230  {
1231  ptDriver->ptDevice.ptSPI->spi_cr1_b.tx_fifo_wm = ptDriver->TxBufferSize - ptDriver->TxBufferCounter;
1232  }
1233  }
1234  if(ptDriver->RxBufferCounter == ptDriver->RxBufferSize && ptDriver->TxBufferCounter == ptDriver->TxBufferSize
1235  && !(ptDriver->ptDevice.ptSPI->spi_sr_b.BSY == 1))
1236  {
1237  if(ptDriver->tConfiguration.eBehaviour == DRV_SPI_BEHAVIOUR_MASTER)
1238  {
1239  if(ptDriver->tConfiguration.eFSSStatic == DRV_SPI_FSS_STATIC_DRIVER)
1240  {
1241  ptDriver->ptDevice.ptSPI->spi_cr1_b.fss = DRV_SPI_FSS_NONE;
1242  }
1243  }
1244  if(ptDriver->tConfiguration.fnCompleteCallback != 0)
1245  {
1246  ptDriver->tConfiguration.fnCompleteCallback(ptDriver, ptDriver->tConfiguration.pCompleteCallbackHandle);
1247  }
1248  ptDriver->TxBuffer = 0;
1249  ptDriver->TxBufferSize = 0;
1250  ptDriver->TxBufferCounter = 0;
1251  ptDriver->RxBuffer = 0;
1252  ptDriver->RxBufferSize = 0;
1253  ptDriver->RxBufferCounter = 0;
1254  ptDriver->ptDevice.ptSPI->spi_imsc = 0;
1255  }
1256  ptDriver->ptDevice.ptSPI->spi_icr = 0xFFFFFFFFul;
1257 }
1258 
1262 #define DRV_SPI_IRQHandler_Generator(id, _) DRV_Default_IRQHandler_Function_Generator(DRV_SPI_IRQ_HANDLER ## id,DRV_SPI_IRQ_Inline_Handler,(DRV_SPI_DEVICE_ID_E)(DRV_SPI_DEVICE_ID_MIN + id))
1263 
1267 /*lint -save -e123 */
1268 DRV_DEF_REPEAT_EVAL(DRV_SPI_DEVICE_COUNT, DRV_SPI_IRQHandler_Generator, ~)
1269 /*lint -restore */
1270 
1271 /* End of group GPIO */
1272 
1273 #endif /* DRV_SPI_MODULE_DISABLED */
DRV_SPI_STATE_E
DRV_SPI_STATE_E
Enumeration of the spi state informations.
Definition: netx_drv_spi.h:288
DRV_DEF_REPEAT_EVAL
#define DRV_DEF_REPEAT_EVAL(...)
Definition: netx_drv.h:234
DRV_SPI_CONFIGURATION_T::eBehaviour
DRV_SPI_BEHAVIOUR_E eBehaviour
Definition: netx_drv_spi.h:329
DRV_SPI_DEVICE_ID_SQI_BORDER
Definition: netx_drv_csp_netx90_app.h:493
DRV_SPI_CONFIGURATION_T::eDuplex
DRV_SPI_DUPLEX_E eDuplex
Definition: netx_drv_spi.h:327
DRV_DMAC_TRANSFER_WIDTH_E
DRV_DMAC_TRANSFER_WIDTH_E
The width of a dmac transfer.
Definition: netx_drv_dmac.h:84
DRV_SPI_STATE_TX_FIFO_UNDERRUN
Definition: netx_drv_spi.h:297
DRV_LOCK_INITIALIZER
#define DRV_LOCK_INITIALIZER
Initializer of the type to be locked as rvalue is in default the mutex initializer.
Definition: netx_drv_conf.h:102
DRV_SPI_DEVICE_ID_QSPI_BORDER
Definition: netx_drv_csp_netx90_app.h:494
DRV_DMAC_CONFIGURATION_T::eDeviceID
DRV_DMAC_DEVICE_ID_E eDeviceID
Definition: netx_drv_dmac.h:190
IRQn_Type
IRQn_Type
Definition: netx90_app.h:57
DRV_SPI_HANDLE_T::TxBuffer
void *volatile TxBuffer
Definition: netx_drv_spi.h:360
sqi_Type::sqi_cr1_b
struct sqi_Type::@4043::@4070 sqi_cr1_b
spi0_app_Type::spi_dr
__IOM uint32_t spi_dr
Definition: netx90_app.h:21150
DRV_SPI_FSS_E
DRV_SPI_FSS_E
Enumeration of the frame or slave select (FSS) signal pin mask.
Definition: netx_drv_spi.h:53
DRV_DMAC_PERIPHERAL_MEMORY
Definition: netx_drv_csp_netx90_app.h:438
DRV_NVIC_DisableIRQ
void DRV_NVIC_DisableIRQ(IRQn_Type IRQn)
This method disables a given interrupt.
Definition: netx_drv_cortex.c:73
DRV_SPI_LOOP_BACK_MODE_ACTIVE
Definition: netx_drv_spi.h:245
sqi_Type::sqi_pio_oe
__IOM uint32_t sqi_pio_oe
Definition: netx90_app.h:16223
sqi_Type::sqi_irq_raw
__IOM uint32_t sqi_irq_raw
Definition: netx90_app.h:16085
DRV_SPI_PARALLELISM_2BIT
Definition: netx_drv_spi.h:141
DRV_SPI_FREQUENCY_STOPPED
Definition: netx_drv_spi.h:69
DRV_DMAC_HANDLE_T::DRV_DMAC_Abort
DRV_STATUS_E DRV_DMAC_Abort(DRV_DMAC_HANDLE_T *const ptSequencer)
Aborts the given dmac sequencer.
Definition: netx_drv_dmac.c:275
DRV_SPI_HANDLE_T::tConfiguration
DRV_SPI_CONFIGURATION_T tConfiguration
Definition: netx_drv_spi.h:358
DRV_SPI_CONFIGURATION_T::eSPIDeviceID
DRV_SPI_DEVICE_ID_E eSPIDeviceID
Definition: netx_drv_spi.h:320
DRV_SPI_DUMMYPATTERN_FULL
Definition: netx_drv_spi.h:257
DRV_SPI_CONFIGURATION_T::eRxFiFoWm
DRV_SPI_FIFO_WM_E eRxFiFoWm
Definition: netx_drv_spi.h:334
DRV_SPI_DEVICE_ID_MAX
Definition: netx_drv_csp_netx90_app.h:492
DRV_SPI_DUMMYPATTERN_NULL
Definition: netx_drv_spi.h:254
DRV_SPI_CONFIGURATION_T::pCompleteCallbackHandle
void * pCompleteCallbackHandle
Definition: netx_drv_spi.h:344
DRV_SPI_Flush_DMA_Callback_Tx
static void DRV_SPI_Flush_DMA_Callback_Tx(void *ptDriverHandle, DRV_SPI_HANDLE_T *const ptDriver)
Definition: netx_drv_spi.c:130
DRV_ERROR_BUFFER
Definition: netx_drv_def.h:63
DRV_SPI_DUPLEX_HALF
Definition: netx_drv_spi.h:128
DRV_SPI_HANDLE_T::RxBufferCounter
size_t volatile RxBufferCounter
Definition: netx_drv_spi.h:365
sqi_Type::sqi_irq_mask
__IOM uint32_t sqi_irq_mask
Definition: netx90_app.h:16057
DRV_NVIC_EnableIRQ
void DRV_NVIC_EnableIRQ(IRQn_Type IRQn)
This method enables a given interrupt.
Definition: netx_drv_cortex.c:64
DRV_SPI_DATA_SIZE_SELECT_MIN
Definition: netx_drv_spi.h:268
DRV_DMAC_INCREMENTATION_INACTIVE
Definition: netx_drv_dmac.h:108
DRV_SPI_CONFIGURATION_T::eFSS
DRV_SPI_FSS_E eFSS
Definition: netx_drv_spi.h:323
DRV_SPI_CONFIGURATION_T::ulDriverTimeout
uint32_t ulDriverTimeout
Definition: netx_drv_spi.h:345
sqi_Type::sqi_dmacr_b
struct sqi_Type::@4059::@4078 sqi_dmacr_b
DRV_SPI_CONFIGURATION_T::eFILTER
DRV_SPI_FILTER_E eFILTER
Definition: netx_drv_spi.h:331
DRV_SPI_CONFIGURATION_T::ptSequencerTx
DRV_DMAC_HANDLE_T * ptSequencerTx
Definition: netx_drv_spi.h:341
DRV_SPI_HANDLE_T::DRV_SPI_Flush_IRQ
static DRV_STATUS_E DRV_SPI_Flush_IRQ(DRV_SPI_HANDLE_T *const ptDriver)
This method shall perform a flush by interrupt mode.
Definition: netx_drv_spi.c:582
DRV_SPI_MODE_U::structure
DRV_SPI_MODE_T structure
Definition: netx_drv_spi.h:174
DRV_DMAC_CONFIGURATION_T::ptCallbackHandleComplete
void * ptCallbackHandleComplete
Definition: netx_drv_dmac.h:197
DRV_DMAC_PERIPHERAL_E
DRV_DMAC_PERIPHERAL_E
Definition: netx_drv_csp_netx90_app.h:404
DRV_SPI_HANDLE_T::DRV_SPI_Flush_DMA
static DRV_STATUS_E DRV_SPI_Flush_DMA(DRV_SPI_HANDLE_T *const ptDriver)
This method shall perform a flush by dma mode.
Definition: netx_drv_spi.c:624
spi0_app_Type::spi_cr0_b
struct spi0_app_Type::@4776::@4802 spi_cr0_b
DRV_TOUT
Definition: netx_drv_def.h:58
DRV_SPI_MODE_T::eSPH
DRV_SPI_SPH_E eSPH
Definition: netx_drv_spi.h:164
DRV_BUSY
Definition: netx_drv_def.h:57
DRV_ERROR
Definition: netx_drv_def.h:56
spi0_app_Type::spi_dmacr
__IOM uint32_t spi_dmacr
Definition: netx90_app.h:21316
DRV_SPI_CONFIGURATION_T::eLoopBackMode
DRV_SPI_LOOP_BACK_MODE_E eLoopBackMode
Definition: netx_drv_spi.h:336
spi0_app_Type::spi_cr1_b
struct spi0_app_Type::@4778::@4803 spi_cr1_b
DRV_SPI_DEVICE_ID_E
DRV_SPI_DEVICE_ID_E
The SPI device IDs.
Definition: netx_drv_csp_netx90_app.h:474
s_apDeviceAddressTable
static DRV_SPI_DEVICE_U const s_apDeviceAddressTable[DRV_SPI_DEVICE_COUNT]
Table of the device addresses.
Definition: netx_drv_spi.c:69
DRV_SPI_HANDLE_T::RxBuffer
void *volatile RxBuffer
Definition: netx_drv_spi.h:363
DRV_SPI_DEVICE_COUNT
#define DRV_SPI_DEVICE_COUNT
Definition: netx_drv_csp_netx90_app.h:511
DRV_IRQ_Enable
__STATIC_INLINE int DRV_IRQ_Enable(void)
This is a semaphore function for nested enabling the interrupts.
Definition: netx_drv_cortex.h:133
DRV_SPI_DATA_SIZE_SELECT_DEFAULT
Definition: netx_drv_spi.h:273
DRV_SPI_FIFO_WM_DEFAULT
Definition: netx_drv_spi.h:205
DRV_SPI_STATE_RX_FIFO_OVERFLOW
Definition: netx_drv_spi.h:291
DRV_DMAC_CONFIGURATION_T::fCallbackComplete
DRV_CALLBACK_F fCallbackComplete
Definition: netx_drv_dmac.h:196
DRV_SPI_CONFIGURATION_T::eFrameFormat
DRV_SPI_FRAME_FORMAT_E eFrameFormat
Definition: netx_drv_spi.h:325
DRV_OPERATION_MODE_POLL
Definition: netx_drv_def.h:71
DRV_OPERATION_MODE_DMA
Definition: netx_drv_def.h:73
sqi_Type::sqi_tcr
__IOM uint32_t sqi_tcr
Definition: netx90_app.h:15999
DRV_LOCK
#define DRV_LOCK(__HANDLE__)
A function calling the trylock of the mutex and returning locked in case it is blocked.
Definition: netx_drv_conf.h:107
DRV_SPI_PARALLELISM_1BIT
Definition: netx_drv_spi.h:140
DRV_SPI_CONFIGURATION_T::eFrequency
DRV_SPI_FREQUENCY_E eFrequency
Definition: netx_drv_spi.h:324
sqi_Type::sqi_cr0_b
struct sqi_Type::@4041::@4069 sqi_cr0_b
DRV_SPI_BEHAVIOUR_MASTER
Definition: netx_drv_spi.h:92
DRV_SPI_HANDLE_T::ptDevice
DRV_SPI_DEVICE_U ptDevice
Definition: netx_drv_spi.h:357
spi0_app_Type::spi_imsc_b
struct spi0_app_Type::@4784::@4806 spi_imsc_b
sqi_Type::sqi_sqirom_cfg
__IOM uint32_t sqi_sqirom_cfg
Definition: netx90_app.h:16257
DRV_DMAC_CONFIGURATION_T::eTransferWidthDest
DRV_DMAC_TRANSFER_WIDTH_E eTransferWidthDest
Definition: netx_drv_dmac.h:193
DRV_SPI_FSS_STATIC_DRIVER
Definition: netx_drv_spi.h:194
DRV_SPI_HANDLE_T::DRV_SPI_Flush_POLL
static DRV_STATUS_E DRV_SPI_Flush_POLL(DRV_SPI_HANDLE_T *const ptDriver)
This method shall perform a flush by polling mode.
Definition: netx_drv_spi.c:532
spi0_app_Type::spi_icr
__IOM uint32_t spi_icr
Definition: netx90_app.h:21292
DRV_SPI_HANDLE_T::DRV_SPI_IRQ_Inline_Handler
__STATIC_INLINE void DRV_SPI_IRQ_Inline_Handler(DRV_SPI_DEVICE_ID_E const eDeviceID)
Definition: netx_drv_spi.c:1199
spi0_app_Type::spi_dmacr_b
struct spi0_app_Type::@4792::@4810 spi_dmacr_b
DRV_SPI_HANDLE_T::TxBufferCounter
size_t volatile TxBufferCounter
Definition: netx_drv_spi.h:362
DRV_DMAC_CONFIGURATION_T::eTransferWidthSource
DRV_DMAC_TRANSFER_WIDTH_E eTransferWidthSource
Definition: netx_drv_dmac.h:192
DRV_DMAC_CONFIGURATION_T::eIncrementationDest
DRV_DMAC_INCREMENTATION_E eIncrementationDest
Definition: netx_drv_dmac.h:195
DRV_SPI_PARALLELISM_4BIT
Definition: netx_drv_spi.h:142
DRV_SPI_BEHAVIOUR_SLAVE
Definition: netx_drv_spi.h:93
DRV_SPI_DEVICE_DMA_LIST
#define DRV_SPI_DEVICE_DMA_LIST
Definition: netx_drv_csp_netx90_app.h:514
netx_drv.h
This file contains all the functions prototypes for the peripheral module driver. ...
sqi_Type::sqi_cr0
__IOM uint32_t sqi_cr0
Definition: netx90_app.h:15819
DRV_DMAC_INCREMENTATION_ACTIVE
Definition: netx_drv_dmac.h:109
DRV_OPERATION_MODE_IRQ
Definition: netx_drv_def.h:72
DRV_SPI_HANDLE_T::DRV_SPI_Abort
DRV_STATUS_E DRV_SPI_Abort(DRV_SPI_HANDLE_T *const ptDriver)
Function for aborting the current data transfer on the SPI device.
Definition: netx_drv_spi.c:1068
sqi_Type::sqi_irq_clear
__IOM uint32_t sqi_irq_clear
Definition: netx90_app.h:16154
DRV_ERROR_PARAM
Definition: netx_drv_def.h:61
spi0_app_Type::spi_sr
__IM uint32_t spi_sr
Definition: netx90_app.h:21178
DRV_SPI_HANDLE_T
The handle of the driver.
Definition: netx_drv_spi.h:355
DRV_SPI_HANDLE_T::TxBufferSize
size_t volatile TxBufferSize
Definition: netx_drv_spi.h:361
DRV_DMAC_HANDLE_T::tConfiguration
DRV_DMAC_CONFIGURATION_T tConfiguration
Definition: netx_drv_dmac.h:211
DRV_SPI_CONFIGURATION_T::ptSequencerRx
DRV_DMAC_HANDLE_T * ptSequencerRx
Definition: netx_drv_spi.h:342
s_apDeviceDmacTable
static DRV_DMAC_PERIPHERAL_E const s_apDeviceDmacTable[DRV_SPI_DEVICE_COUNT]
Table of the dma channels of the devices.
Definition: netx_drv_spi.c:74
DRV_SPI_HANDLE_T::DRV_SPI_Flush_Buffers
__STATIC_INLINE DRV_STATUS_E DRV_SPI_Flush_Buffers(DRV_SPI_HANDLE_T *const ptDriver)
This function shall flush the software and hardware buffers of the device.
Definition: netx_drv_spi.c:424
UNUSED
#define UNUSED(x)
If there is the need to outsmart the compiler or linter.
Definition: netx_drv_def.h:40
spi0_app_Type::spi_imsc
__IOM uint32_t spi_imsc
Definition: netx90_app.h:21207
DRV_SPI_DEVICE_U::ptSQI
DRV_SQI_DEVICE_T * ptSQI
Definition: netx_drv_csp_netx90_app.h:502
DRV_SPI_HANDLE_T::DRV_SPI_DeInit
DRV_STATUS_E DRV_SPI_DeInit(DRV_SPI_HANDLE_T *const ptDriver)
This function disables the DRV_SPI_HANDLE_T object.
Definition: netx_drv_spi.c:397
DRV_SPI_HANDLE_T::DRV_SPI_ChangeFss
DRV_STATUS_E DRV_SPI_ChangeFss(DRV_SPI_HANDLE_T *const ptDriver, DRV_SPI_FSS_E eFss)
Function for changing the fss between transactions.
Definition: netx_drv_spi.c:1031
DRV_SPI_CONFIGURATION_T::eDataSize
DRV_SPI_DATA_SIZE_SELECT_E eDataSize
Definition: netx_drv_spi.h:337
DRV_SPI_CONFIGURATION_T::uMode
DRV_SPI_MODE_U uMode
Definition: netx_drv_spi.h:326
DRV_CALLBACK_F
void(* DRV_CALLBACK_F)(void *pvDriverHandle, void *pvUserHandle)
The definition of callbacks used in the driver.
Definition: netx_drv_def.h:48
DRV_SPI_DEVICE_U::ptSPI
DRV_SPI_DEVICE_T * ptSPI
Definition: netx_drv_csp_netx90_app.h:501
DRV_STATUS_E
DRV_STATUS_E
DRV Status structures definition.
Definition: netx_drv_def.h:53
DRV_SPI_HANDLE_T::DRV_SPI_GetState
DRV_STATUS_E DRV_SPI_GetState(DRV_SPI_HANDLE_T *const ptDriver, DRV_SPI_STATE_E *const ptState)
Function returning a driver spi state enumeration and a return code.
Definition: netx_drv_spi.c:1159
DRV_SPI_HANDLE_T::DRV_SPI_Receive
DRV_STATUS_E DRV_SPI_Receive(DRV_SPI_HANDLE_T *const ptDriver, uint8_t *pcData, size_t size)
Function for receiveing data of given size by the SPI device.
Definition: netx_drv_spi.c:840
DRV_SPI_CONFIGURATION_T::eFSSStatic
DRV_SPI_FSS_STATIC_E eFSSStatic
Definition: netx_drv_spi.h:333
DRV_SPI_HANDLE_T::RxBufferSize
size_t volatile RxBufferSize
Definition: netx_drv_spi.h:364
spi0_app_Type::spi_cr0
__IOM uint32_t spi_cr0
Definition: netx90_app.h:21052
DRV_SPI_CONFIGURATION_T::eParallelism
DRV_SPI_PARALLELISM_E eParallelism
Definition: netx_drv_spi.h:328
DRV_SPI_DEVICE_U
Definition: netx_drv_csp_netx90_app.h:498
s_apHandleIRQnTable
static IRQn_Type const s_apHandleIRQnTable[DRV_SPI_DEVICE_COUNT]
Table of the IRQ vector numbers.
Definition: netx_drv_spi.c:80
DRV_DMAC_TRANSFER_WIDTH_8b
Definition: netx_drv_dmac.h:86
spi0_app_Type::spi_sr_b
struct spi0_app_Type::@4782::@4805 spi_sr_b
DRV_SPI_CONFIGURATION_T::eOperationMode
DRV_OPERATION_MODE_E eOperationMode
Definition: netx_drv_spi.h:322
DRV_SPI_FSS_NONE
Definition: netx_drv_spi.h:55
DRV_SPI_FIFO_WM_RESET
Definition: netx_drv_spi.h:203
DRV_SPI_CONFIGURATION_T::uDummyPattern
DRV_SPI_DUMMYPATTERN_E uDummyPattern
Definition: netx_drv_spi.h:338
DRV_NVIC_ClearPendingIRQ
void DRV_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
This method clears the pending state of a given interrupt.
Definition: netx_drv_cortex.c:143
DRV_DMAC_HANDLE_T::DRV_DMAC_Start
DRV_STATUS_E DRV_DMAC_Start(DRV_DMAC_HANDLE_T *const ptSequencer, void *const ptBufferSource, void *const ptBufferDestination, size_t size)
Starts the given dmac sequencer.
Definition: netx_drv_dmac.c:209
DRV_HANDLE_CHECK
#define DRV_HANDLE_CHECK(handle)
Definition: netx_drv_spi.c:92
s_apHandleAddressTable
static DRV_SPI_HANDLE_T * s_apHandleAddressTable[DRV_SPI_DEVICE_COUNT]
Used for mapping the handle to an interrupt.
Definition: netx_drv_spi.c:86
spi0_app_Type::spi_cr1
__IOM uint32_t spi_cr1
Definition: netx90_app.h:21107
DRV_DMAC_HANDLE_T::DRV_DMAC_Init
DRV_STATUS_E DRV_DMAC_Init(DRV_DMAC_HANDLE_T *const ptSequencer)
Initializes the dmac sequencer and its handle by the given configuration.
Definition: netx_drv_dmac.c:86
DRV_SPI_CONFIGURATION_T::eSlaveSigEarly
DRV_SPI_SLV_SIG_EARLY_E eSlaveSigEarly
Definition: netx_drv_spi.h:330
DRV_SPI_HANDLE_T::DRV_SPI_Init
DRV_STATUS_E DRV_SPI_Init(DRV_SPI_HANDLE_T *const ptDriver)
This function initializes the DRV_SPI_HANDLE_T object.
Definition: netx_drv_spi.c:167
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
DRV_SPI_HANDLE_T::DRV_SPI_TransmitReceive
DRV_STATUS_E DRV_SPI_TransmitReceive(DRV_SPI_HANDLE_T *const ptDriver, uint8_t *txData, uint8_t *rxData, size_t size)
Function for transmitting and receiveing data at the same time of given size by the SPI device...
Definition: netx_drv_spi.c:956
DRV_SPI_DATA_SIZE_SELECT_RESET
Definition: netx_drv_spi.h:266
DRV_UNLOCK
#define DRV_UNLOCK(__HANDLE__)
The release function used.
Definition: netx_drv_conf.h:112
DRV_DMAC_CONFIGURATION_T::eIncrementationSource
DRV_DMAC_INCREMENTATION_E eIncrementationSource
Definition: netx_drv_dmac.h:194
DRV_SPI_DATA_SIZE_SELECT_8b
Definition: netx_drv_spi.h:272
DRV_SPI_IRQHandler_Generator
#define DRV_SPI_IRQHandler_Generator(id, _)
Definition: netx_drv_spi.c:1262
DRV_SPI_DEVICE_LIST
#define DRV_SPI_DEVICE_LIST
Definition: netx_drv_csp_netx90_app.h:512
sqi_Type::sqi_dmacr
__IOM uint32_t sqi_dmacr
Definition: netx90_app.h:16177
DRV_SPI_STATE_TX_FIFO_OVERFLOW
Definition: netx_drv_spi.h:298
DRV_SPI_HANDLE_T::DRV_SPI_Transmit
DRV_STATUS_E DRV_SPI_Transmit(DRV_SPI_HANDLE_T *const ptDriver, uint8_t *pcData, size_t size)
Function for transmitting data of given size via the SPI device.
Definition: netx_drv_spi.c:723
DRV_SPI_STATE_RX_FIFO_UNDERRUN
Definition: netx_drv_spi.h:290
DRV_OK
Definition: netx_drv_def.h:55
DRV_SPI_MODE_T::eSPO
DRV_SPI_SPO_E eSPO
Definition: netx_drv_spi.h:165
DRV_SPI_CONFIGURATION_T::eTxFiFoWm
DRV_SPI_FIFO_WM_E eTxFiFoWm
Definition: netx_drv_spi.h:335
DRV_SPI_DEVICE_IRQ_LIST
#define DRV_SPI_DEVICE_IRQ_LIST
Definition: netx_drv_csp_netx90_app.h:513
DRV_SPI_DEVICE_ID_MIN
Definition: netx_drv_csp_netx90_app.h:491
sqi_Type::sqi_irq_mask_b
struct sqi_Type::@4051::@4074 sqi_irq_mask_b
sqi_Type::sqi_pio_out
__IOM uint32_t sqi_pio_out
Definition: netx90_app.h:16203
DRV_SPI_MISO_INACTIVE
Definition: netx_drv_spi.h:45
sqi_Type::sqi_cr1
__IOM uint32_t sqi_cr1
Definition: netx90_app.h:15870
DRV_IRQ_Disable
__STATIC_INLINE int DRV_IRQ_Disable(void)
This is a semaphore function for nested disabling the interrupts.
Definition: netx_drv_cortex.h:154
DRV_DMAC_CONFIGURATION_T::ePeripheralSource
DRV_DMAC_PERIPHERAL_E ePeripheralSource
Definition: netx_drv_dmac.h:198
DRV_SPI_DATA_SIZE_SELECT_MAX
Definition: netx_drv_spi.h:282
DRV_SPI_FIFO_WM_MIN
Definition: netx_drv_spi.h:204
DRV_SPI_Flush_DMA_Callback_Rx
static void DRV_SPI_Flush_DMA_Callback_Rx(void *ptDriverHandle, DRV_SPI_HANDLE_T *const ptDriver)
Definition: netx_drv_spi.c:107
DRV_SPI_HANDLE_T::tLock
DRV_LOCK_T tLock
Definition: netx_drv_spi.h:366
sqi_Type::sqi_tcr_b
struct sqi_Type::@4049::@4073 sqi_tcr_b
DRV_DMAC_TRANSFER_WIDTH_16b
Definition: netx_drv_dmac.h:87
DRV_SPI_FSS_STATIC_HARDWARE
Definition: netx_drv_spi.h:193
DRV_SPI_CONFIGURATION_T::eMISO
DRV_SPI_MISO_E eMISO
Definition: netx_drv_spi.h:321
DRV_SPI_DUPLEX_FULL
Definition: netx_drv_spi.h:129
DRV_SPI_HANDLE_T::ullFrameStartTick
uint64_t ullFrameStartTick
Definition: netx_drv_spi.h:359
DRV_SPI_DEVICE_U::pt
uintptr_t pt
Definition: netx_drv_csp_netx90_app.h:500
DRV_NSUPP
Definition: netx_drv_def.h:59
DRV_SPI_CONFIGURATION_T::eDMARx
DRV_DMAC_DEVICE_ID_E eDMARx
Definition: netx_drv_spi.h:340
DRV_SPI_CONFIGURATION_T::eDMATx
DRV_DMAC_DEVICE_ID_E eDMATx
Definition: netx_drv_spi.h:339
DRV_DMAC_CONFIGURATION_T::ePeripheralDest
DRV_DMAC_PERIPHERAL_E ePeripheralDest
Definition: netx_drv_dmac.h:199
DRV_SPI_CONFIGURATION_T::fnCompleteCallback
DRV_CALLBACK_F fnCompleteCallback
Definition: netx_drv_spi.h:343