Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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trigger_irq_app (trigger_irq_app) More...
#include <netx90_app.h>
Data Fields | |
union { | |
__IOM uint32_t trigger_irq_cfg | |
struct { | |
__IOM uint32_t xc_trigger_out_polarity: 2 | |
__IOM uint32_t bf_align0: 30 | |
} trigger_irq_cfg_b | |
}; | |
union { | |
__IOM uint32_t trigger_irq_raw | |
struct { | |
__IOM uint32_t xc_trigger_out_edge: 2 | |
__IOM uint32_t bf_align0: 30 | |
} trigger_irq_raw_b | |
}; | |
union { | |
__IM uint32_t trigger_irq_masked | |
struct { | |
__IM uint32_t xc_trigger_out_edge: 2 | |
__IM uint32_t bf_align0: 30 | |
} trigger_irq_masked_b | |
}; | |
union { | |
__IOM uint32_t trigger_irq_msk_set | |
struct { | |
__IOM uint32_t xc_trigger_out_edge: 2 | |
__IOM uint32_t bf_align0: 30 | |
} trigger_irq_msk_set_b | |
}; | |
union { | |
__IOM uint32_t trigger_irq_msk_reset | |
struct { | |
__IOM uint32_t xc_trigger_out_edge: 2 | |
__IOM uint32_t bf_align0: 30 | |
} trigger_irq_msk_reset_b | |
}; | |
trigger_irq_app (trigger_irq_app)
Definition at line 25685 of file netx90_app.h.
union { ... } |
< (@ 0xFF801720) trigger_irq_app Structure
union { ... } |
union { ... } |
union { ... } |
union { ... } |
__IOM uint32_t trigger_irq_app_Type::bf_align0 |
[31..2] bitField alignment value for aeabi compatibility
Definition at line 25697 of file netx90_app.h.
__IM uint32_t trigger_irq_app_Type::bf_align0 |
[31..2] bitField alignment value for aeabi compatibility
Definition at line 25720 of file netx90_app.h.
__IOM uint32_t trigger_irq_app_Type::trigger_irq_cfg |
(@ 0x00000000) Trigger IRQ configuration register.
Definition at line 25688 of file netx90_app.h.
struct { ... } trigger_irq_app_Type::trigger_irq_cfg_b |
__IM uint32_t trigger_irq_app_Type::trigger_irq_masked |
(@ 0x00000008) Trigger masked IRQ: Shows status of masked IRQs.
Definition at line 25716 of file netx90_app.h.
struct { ... } trigger_irq_app_Type::trigger_irq_masked_b |
__IOM uint32_t trigger_irq_app_Type::trigger_irq_msk_reset |
(@ 0x00000010) Trigger IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 25744 of file netx90_app.h.
struct { ... } trigger_irq_app_Type::trigger_irq_msk_reset_b |
__IOM uint32_t trigger_irq_app_Type::trigger_irq_msk_set |
(@ 0x0000000C) Trigger IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to bod_irq_raw.
Definition at line 25725 of file netx90_app.h.
struct { ... } trigger_irq_app_Type::trigger_irq_msk_set_b |
__IOM uint32_t trigger_irq_app_Type::trigger_irq_raw |
(@ 0x00000004) Trigger raw IRQ: Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ. Write access with '0' does not influence this bit.
Definition at line 25702 of file netx90_app.h.
struct { ... } trigger_irq_app_Type::trigger_irq_raw_b |
__IOM uint32_t trigger_irq_app_Type::xc_trigger_out_edge |
[1..0] Edge detected on xc_trigger_out.
Definition at line 25710 of file netx90_app.h.
__IM uint32_t trigger_irq_app_Type::xc_trigger_out_edge |
[1..0] Edge detected on xc_trigger_out.
Definition at line 25719 of file netx90_app.h.
__IOM uint32_t trigger_irq_app_Type::xc_trigger_out_polarity |
[1..0] Polarity of xc_trigger_out signals for edge detection. 0: Use pos-edge on xc_trigger_out signals to trigger an IRQ. 1: Use neg-edge on xc_trigger_out signals to trigger an IRQ. Note: Changing the polarity will trigger set an IRQ in the raw register (and when the mask is set also the IRQ signal to the CPU) due to the edge detection logic.
Definition at line 25691 of file netx90_app.h.