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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
nfifo (nfifo) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IOM uint32_t nfifo_config | |
| struct { | |
| __IOM uint32_t bf_align0: 2 | |
| __IOM uint32_t base_config: 30 | |
| } nfifo_config_b | |
| }; | |
| __IM uint32_t | RESERVED [2] |
| union { | |
| __IOM uint32_t nfifo_irq_raw | |
| struct { | |
| __IOM uint32_t ahbl_error: 1 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t fifo_active: 1 | |
| __IOM uint32_t observe0: 1 | |
| __IOM uint32_t observe1: 1 | |
| __IOM uint32_t observe2: 1 | |
| __IOM uint32_t observe3: 1 | |
| __IOM uint32_t observe4: 1 | |
| __IOM uint32_t observe5: 1 | |
| __IOM uint32_t observe6: 1 | |
| __IOM uint32_t observe7: 1 | |
| __IOM uint32_t observe8: 1 | |
| __IOM uint32_t observe9: 1 | |
| __IOM uint32_t bf_align0: 18 | |
| } nfifo_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t nfifo_irq_arm_app_masked | |
| struct { | |
| __IM uint32_t ahbl_error: 1 | |
| __IM uint32_t read: 1 | |
| __IM uint32_t write: 1 | |
| __IM uint32_t fifo_active: 1 | |
| __IM uint32_t observe0: 1 | |
| __IM uint32_t observe1: 1 | |
| __IM uint32_t observe2: 1 | |
| __IM uint32_t observe3: 1 | |
| __IM uint32_t observe4: 1 | |
| __IM uint32_t observe5: 1 | |
| __IM uint32_t observe6: 1 | |
| __IM uint32_t observe7: 1 | |
| __IM uint32_t observe8: 1 | |
| __IM uint32_t observe9: 1 | |
| __IM uint32_t bf_align0: 18 | |
| } nfifo_irq_arm_app_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_arm_app_msk_set | |
| struct { | |
| __IOM uint32_t ahbl_error: 1 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t fifo_active: 1 | |
| __IOM uint32_t observe0: 1 | |
| __IOM uint32_t observe1: 1 | |
| __IOM uint32_t observe2: 1 | |
| __IOM uint32_t observe3: 1 | |
| __IOM uint32_t observe4: 1 | |
| __IOM uint32_t observe5: 1 | |
| __IOM uint32_t observe6: 1 | |
| __IOM uint32_t observe7: 1 | |
| __IOM uint32_t observe8: 1 | |
| __IOM uint32_t observe9: 1 | |
| __IOM uint32_t bf_align0: 18 | |
| } nfifo_irq_arm_app_msk_set_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_arm_app_msk_reset | |
| struct { | |
| __IOM uint32_t ahbl_error: 1 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t fifo_active: 1 | |
| __IOM uint32_t observe0: 1 | |
| __IOM uint32_t observe1: 1 | |
| __IOM uint32_t observe2: 1 | |
| __IOM uint32_t observe3: 1 | |
| __IOM uint32_t observe4: 1 | |
| __IOM uint32_t observe5: 1 | |
| __IOM uint32_t observe6: 1 | |
| __IOM uint32_t observe7: 1 | |
| __IOM uint32_t observe8: 1 | |
| __IOM uint32_t observe9: 1 | |
| __IOM uint32_t bf_align0: 18 | |
| } nfifo_irq_arm_app_msk_reset_b | |
| }; | |
| __IM uint32_t | RESERVED1 [3] |
| union { | |
| __IM uint32_t nfifo_irq_xpic_app_masked | |
| struct { | |
| __IM uint32_t ahbl_error: 1 | |
| __IM uint32_t read: 1 | |
| __IM uint32_t write: 1 | |
| __IM uint32_t fifo_active: 1 | |
| __IM uint32_t observe0: 1 | |
| __IM uint32_t observe1: 1 | |
| __IM uint32_t observe2: 1 | |
| __IM uint32_t observe3: 1 | |
| __IM uint32_t observe4: 1 | |
| __IM uint32_t observe5: 1 | |
| __IM uint32_t observe6: 1 | |
| __IM uint32_t observe7: 1 | |
| __IM uint32_t observe8: 1 | |
| __IM uint32_t observe9: 1 | |
| __IM uint32_t bf_align0: 18 | |
| } nfifo_irq_xpic_app_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_xpic_app_msk_set | |
| struct { | |
| __IOM uint32_t ahbl_error: 1 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t fifo_active: 1 | |
| __IOM uint32_t observe0: 1 | |
| __IOM uint32_t observe1: 1 | |
| __IOM uint32_t observe2: 1 | |
| __IOM uint32_t observe3: 1 | |
| __IOM uint32_t observe4: 1 | |
| __IOM uint32_t observe5: 1 | |
| __IOM uint32_t observe6: 1 | |
| __IOM uint32_t observe7: 1 | |
| __IOM uint32_t observe8: 1 | |
| __IOM uint32_t observe9: 1 | |
| __IOM uint32_t bf_align0: 18 | |
| } nfifo_irq_xpic_app_msk_set_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_xpic_app_msk_reset | |
| struct { | |
| __IOM uint32_t ahbl_error: 1 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t fifo_active: 1 | |
| __IOM uint32_t observe0: 1 | |
| __IOM uint32_t observe1: 1 | |
| __IOM uint32_t observe2: 1 | |
| __IOM uint32_t observe3: 1 | |
| __IOM uint32_t observe4: 1 | |
| __IOM uint32_t observe5: 1 | |
| __IOM uint32_t observe6: 1 | |
| __IOM uint32_t observe7: 1 | |
| __IOM uint32_t observe8: 1 | |
| __IOM uint32_t observe9: 1 | |
| __IOM uint32_t bf_align0: 18 | |
| } nfifo_irq_xpic_app_msk_reset_b | |
| }; | |
| __IM uint32_t | RESERVED2 [9] |
| union { | |
| __IOM uint32_t nfifo_irq_observe0 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe0_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe1 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe1_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe2 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe2_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe3 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe3_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe4 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe4_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe5 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe5_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe6 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe6_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe7 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe7_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe8 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe8_b | |
| }; | |
| union { | |
| __IOM uint32_t nfifo_irq_observe9 | |
| struct { | |
| __IOM uint32_t fifonr: 10 | |
| __IOM uint32_t bf_align0: 5 | |
| __IOM uint32_t read: 1 | |
| __IOM uint32_t undr: 1 | |
| __IOM uint32_t emw: 1 | |
| __IOM uint32_t empty: 1 | |
| __IOM uint32_t write: 1 | |
| __IOM uint32_t ovfl: 1 | |
| __IOM uint32_t fmw: 1 | |
| __IOM uint32_t full: 1 | |
| __IOM uint32_t bf_align1: 9 | |
| } nfifo_irq_observe9_b | |
| }; | |
| union { | |
| __IOM uint32_t * nfifo_fifo_start | |
| struct { | |
| __IOM uint32_t bf_align0: 32 | |
| } nfifo_fifo_start_b | |
| }; | |
| __IM uint32_t | RESERVED3 [990] |
| union { | |
| __IOM uint32_t * nfifo_fifo_end | |
| struct { | |
| __IOM uint32_t bf_align0: 32 | |
| } nfifo_fifo_end_b | |
| }; | |
nfifo (nfifo)
Definition at line 10422 of file netx90_app.h.
| union { ... } |
< (@ 0xFF400000) nfifo Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IOM uint32_t nfifo_Type::ahbl_error |
[0..0] AHBL returned HRESP=1 (abort)
Definition at line 10453 of file netx90_app.h.
| __IM uint32_t nfifo_Type::ahbl_error |
[0..0] AHBL returned HRESP=1 (abort)
Definition at line 10478 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::base_config |
[31..2] Pointer to base_config
Definition at line 10439 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::bf_align0 |
[1..0] bitField alignment value for aeabi compatibility
[31..14] bitField alignment value for aeabi compatibility
[14..10] bitField alignment value for aeabi compatibility
[31..0] bitField alignment value for aeabi compatibility
Definition at line 10438 of file netx90_app.h.
| __IM uint32_t nfifo_Type::bf_align0 |
[31..14] bitField alignment value for aeabi compatibility
Definition at line 10493 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::bf_align1 |
[31..23] bitField alignment value for aeabi compatibility
Definition at line 10665 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::empty |
[18..18] Activate IRQ in case of FIFO gets empty
Definition at line 10660 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::emw |
[17..17] Activate IRQ in case of Empty-Minus-Watermark is set
Definition at line 10659 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::fifo_active |
[3..3] any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
Definition at line 10456 of file netx90_app.h.
| __IM uint32_t nfifo_Type::fifo_active |
[3..3] any access to fifo_nr/fifo_wr is active (to unlock the scheduler after locking_req)
Definition at line 10481 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::fifonr |
[9..0] Number of FIFO to be observed
Definition at line 10655 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::fmw |
[21..21] Activate IRQ in case of Full-Minus-Watermark is set
Definition at line 10663 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::full |
[22..22] Activate IRQ in case of FIFO gets full
Definition at line 10664 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::nfifo_config |
(@ 0x00000000) NFIFO config register 'base_config' is a pointer to start of NFIFO configuration area in memory. The configuration area must be setup by software, before using a FIFO. Each FIFO-configuration entry consists of 3 DW and contains the following: { | mem-DW0: base(31:2),mas(1:0) mem-DW1: watm(28:16),bottom(12:0) mem-DW2: undr(31),emw(30),empty(29),write(28:16),ovfl(15),fmw(14),f ll(13),fill(12:0) } This allows FIFOs of up to 8k entries each. The first DWords mem-DW0 and mem-DW1 are only re
Definition at line 10425 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_config_b |
| __IOM uint32_t* nfifo_Type::nfifo_fifo_end |
(@ 0x00000FFC) End of NFIFO FIFO access addresses
Definition at line 10866 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_fifo_end_b |
| __IOM uint32_t* nfifo_Type::nfifo_fifo_start |
(@ 0x00000080) Start of NFIFO FIFO access addresses: The following DW-addresses are associated with FIFOs: Read accesses to an address in this area are reading from the appropriate FIFO, write accesses to an address in this area are writing to the appropriate FIFO. The number of FIFOs is limited by this address area to 991.
Definition at line 10850 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_fifo_start_b |
| __IM uint32_t nfifo_Type::nfifo_irq_arm_app_masked |
(@ 0x00000010) Masked IRQ of ARM_APP: Shows status of masked IRQs as connected to application ARM Cortex M4.
Definition at line 10473 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_arm_app_masked_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_arm_app_msk_reset |
(@ 0x00000018) ARM_APP Cortex M4 IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 10532 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_arm_app_msk_reset_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_arm_app_msk_set |
(@ 0x00000014) ARM_APP Cortex M4 IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources to the ARM_APP processor. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing
Definition at line 10498 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_arm_app_msk_set_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe0 |
(@ 0x00000058) FIFO OBSERVE0: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10650 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe0_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe1 |
(@ 0x0000005C) FIFO OBSERVE1: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10670 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe1_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe2 |
(@ 0x00000060) FIFO OBSERVE2: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10690 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe2_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe3 |
(@ 0x00000064) FIFO OBSERVE3: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10710 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe3_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe4 |
(@ 0x00000068) FIFO OBSERVE4: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10730 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe4_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe5 |
(@ 0x0000006C) FIFO OBSERVE5: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10750 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe5_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe6 |
(@ 0x00000070) FIFO OBSERVE6: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10770 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe6_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe7 |
(@ 0x00000074) FIFO OBSERVE7: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10790 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe7_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe8 |
(@ 0x00000078) FIFO OBSERVE8: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10810 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe8_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_observe9 |
(@ 0x0000007C) FIFO OBSERVE9: This register configures the observation unit that allows to observe one FIFO for special events
Definition at line 10830 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_observe9_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_raw |
(@ 0x0000000C) Raw IRQ: Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ. Write access with '0' does not influence this bit.
Definition at line 10445 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_raw_b |
| __IM uint32_t nfifo_Type::nfifo_irq_xpic_app_masked |
(@ 0x00000028) Masked IRQ of xPIC_APP: Shows status of masked IRQs as connected to xPIC_APP.
Definition at line 10562 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_xpic_app_masked_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_xpic_app_msk_reset |
(@ 0x00000030) xPIC_APP IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 10620 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_xpic_app_msk_reset_b |
| __IOM uint32_t nfifo_Type::nfifo_irq_xpic_app_msk_set |
(@ 0x0000002C) xPIC_APP IRQ mask set: The xPIC_APP IRQ mask enables interrupt requests for corresponding interrupt sources to the xPIC_APP processor. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writin
Definition at line 10586 of file netx90_app.h.
| struct { ... } nfifo_Type::nfifo_irq_xpic_app_msk_set_b |
| __IOM uint32_t nfifo_Type::observe0 |
[4..4] access to FIFO as defined in observe0
Definition at line 10458 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe0 |
[4..4] access to FIFO as defined in observe0
Definition at line 10483 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe1 |
[5..5] access to FIFO as defined in observe1
Definition at line 10459 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe1 |
[5..5] access to FIFO as defined in observe1
Definition at line 10484 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe2 |
[6..6] access to FIFO as defined in observe2
Definition at line 10460 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe2 |
[6..6] access to FIFO as defined in observe2
Definition at line 10485 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe3 |
[7..7] access to FIFO as defined in observe3
Definition at line 10461 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe3 |
[7..7] access to FIFO as defined in observe3
Definition at line 10486 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe4 |
[8..8] access to FIFO as defined in observe4
Definition at line 10462 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe4 |
[8..8] access to FIFO as defined in observe4
Definition at line 10487 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe5 |
[9..9] access to FIFO as defined in observe5
Definition at line 10463 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe5 |
[9..9] access to FIFO as defined in observe5
Definition at line 10488 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe6 |
[10..10] access to FIFO as defined in observe6
Definition at line 10464 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe6 |
[10..10] access to FIFO as defined in observe6
Definition at line 10489 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe7 |
[11..11] access to FIFO as defined in observe7
Definition at line 10465 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe7 |
[11..11] access to FIFO as defined in observe7
Definition at line 10490 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe8 |
[12..12] access to FIFO as defined in observe8
Definition at line 10466 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe8 |
[12..12] access to FIFO as defined in observe8
Definition at line 10491 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::observe9 |
[13..13] access to FIFO as defined in observe9
Definition at line 10467 of file netx90_app.h.
| __IM uint32_t nfifo_Type::observe9 |
[13..13] access to FIFO as defined in observe9
Definition at line 10492 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::ovfl |
[20..20] Activate IRQ in case of FIFO overflow
Definition at line 10662 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::read |
[1..1] any read access happened to any FIFO
[15..15] Activate IRQ in case of any read access
Definition at line 10454 of file netx90_app.h.
| __IM uint32_t nfifo_Type::read |
[1..1] any read access happened to any FIFO
Definition at line 10479 of file netx90_app.h.
| __IM uint32_t nfifo_Type::RESERVED[2] |
Definition at line 10442 of file netx90_app.h.
| __IM uint32_t nfifo_Type::RESERVED1[3] |
Definition at line 10559 of file netx90_app.h.
| __IM uint32_t nfifo_Type::RESERVED2[9] |
Definition at line 10647 of file netx90_app.h.
| __IM uint32_t nfifo_Type::RESERVED3[990] |
Definition at line 10863 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::undr |
[16..16] Activate IRQ in case of FIFO underrun
Definition at line 10658 of file netx90_app.h.
| __IOM uint32_t nfifo_Type::write |
[2..2] any write access happened to any FIFO
[19..19] Activate IRQ in case of any write access
Definition at line 10455 of file netx90_app.h.
| __IM uint32_t nfifo_Type::write |
[2..2] any write access happened to any FIFO
Definition at line 10480 of file netx90_app.h.
1.8.11