hif_sdram_ctrl (hif_sdram_ctrl) More...

#include <netx90_app.h>

Collaboration diagram for hif_sdram_ctrl_Type:

Data Fields
union {
__IOM uint32_t sdram_general_ctrl

struct {
__IOM uint32_t banks: 2

__IOM uint32_t bf_align0: 2

__IOM uint32_t rows: 2

__IOM uint32_t bf_align1: 2

__IOM uint32_t columns: 3

__IOM uint32_t bf_align2: 5

__IOM uint32_t dbus16: 1

__IOM uint32_t sdram_pwdn: 1

__IOM uint32_t extclk_en: 1

__IOM uint32_t ctrl_en: 1

__IOM uint32_t bf_align3: 4

__IOM uint32_t refresh_mode: 2

__IOM uint32_t bf_align4: 4

__IOM uint32_t sdram_ready: 1

__IOM uint32_t refresh_status: 1

} sdram_general_ctrl_b

};

union {
__IOM uint32_t sdram_timing_ctrl

struct {
__IOM uint32_t t_RCD: 2

__IOM uint32_t bf_align0: 2

__IOM uint32_t t_WR: 2

__IOM uint32_t t_RP: 2

__IOM uint32_t t_RAS: 3

__IOM uint32_t bf_align1: 1

__IOM uint32_t t_RFC: 4

__IOM uint32_t t_REFI: 2

__IOM uint32_t bf_align2: 2

__IOM uint32_t mem_sdclk_phase: 3

__IOM uint32_t bf_align3: 1

__IOM uint32_t data_sample_phase: 3

__IOM uint32_t bf_align4: 1

__IOM uint32_t bypass_neg_delay: 1

__IOM uint32_t bf_align5: 3

} sdram_timing_ctrl_b

};

union {
__IOM uint32_t sdram_mr

struct {
__IOM uint32_t MR: 14

__IOM uint32_t bf_align0: 18

} sdram_mr_b

};

Detailed Description

hif_sdram_ctrl (hif_sdram_ctrl)

Definition at line 15548 of file netx90_app.h.

Field Documentation

union { ... }

< (@ 0xFF401540) hif_sdram_ctrl Structure

union { ... }

__IOM uint32_t hif_sdram_ctrl_Type::banks

[1..0] Number of SDRAM device banks and address lines. 00 : 2 banks, address (BA0) 01 : 4 banks, address lines (BA1, BA0)(default) All others: reserved

Definition at line 15559 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align0

[3..2] bitField alignment value for aeabi compatibility

[31..14] bitField alignment value for aeabi compatibility

Definition at line 15562 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align1

[7..6] bitField alignment value for aeabi compatibility

[11..11] bitField alignment value for aeabi compatibility

Definition at line 15566 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align2

[15..11] bitField alignment value for aeabi compatibility

[19..18] bitField alignment value for aeabi compatibility

Definition at line 15573 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align3

[23..20] bitField alignment value for aeabi compatibility

[23..23] bitField alignment value for aeabi compatibility

Definition at line 15592 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align4

[29..26] bitField alignment value for aeabi compatibility

[27..27] bitField alignment value for aeabi compatibility

Definition at line 15603 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bf_align5

[31..29] bitField alignment value for aeabi compatibility

Definition at line 15694 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::bypass_neg_delay

[28..28] Bypass data sample clock phase shift. 0: use phase shifted (negative delayed) SDRAM loopback clock for data sampling. 1: bypass phase shift logic for SDRAM data sampling. Use SDRAM loopback clock for data sampling. Bypass must be used for system clock frequencies <= 80MHz (rate_mull_add <= 0xC0). If this bit is programmed with '0' by software but system clock frequency is below 80MHz, it will be changed to '1' to enable bypass automatically. When system frequency is changed to a rate more than 80MHz, the b

Definition at line 15685 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::columns

[10..8] Number of SDRAM device columns and address lines. 000 : 256 columns, address lines A0..A7 (default) 001 : 512 columns, address lines A0..A8 010 : 1k columns, address lines A0..A9 011 : 2k columns, address lines A0..A9,A11 100 : 4k columns, address lines A0..A9,A11,A12 All others: reserved

Definition at line 15567 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::ctrl_en

[19..19] Global SDRAM controller enable. Note: The sdram_timing_ctrl and the sdram_mr register can only be changed while this bit is 0. Initializing and enabling SDRAM should be done as follows: { | A. Special attention must be done before enabling SDRAM after netX reset without power supply was disabled (e.g. pressing some kind of reset button). In this case a reset could be done while a SDRAM read burst was performed. As SDRAM clock will be disabled immediately in case of reset external SDRAM device will keep dr

Definition at line 15583 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::data_sample_phase

[26..24] Data sample clock phase shift. 0..5: adjustable phase-shift for data sampling SDRAM loopback clock (clk_sdloopback) depending on external capacitive load and SDRAM access time (t_AC). The phase can be shifted in 1.25ns steps. clk_sdloopback will internally rise (sample SDRAM read data) at the data_sample_phase+4th clk400 edge after rise of external MEM_SDCLK (including external capacitive load). For correct settings, the delays depending on external capacitive have to be respected. Data sampling has to be

Definition at line 15674 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::dbus16

[16..16] SDRAM data bus width 0 : SDRAM data bus is 8 bit wide (default) 1 : SDRAM data bus is 16 bit wide

Definition at line 15574 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::extclk_en

[18..18] external SDRAM clock enable 0 : SDRAM clock disabled (default) 1 : SDRAM clock enabled Note: The external SDRAM clock will not run if the controller is disabled.

Definition at line 15580 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::mem_sdclk_phase

[22..20] MEM_SDCLK phase shift. 0..5: adjustable phase-shift for external SDRAM clock depending on external capacitive load on MEM_SDCLK-signal to match SDRAM signals setup times. The phase can be shifted in 1.25ns steps. MEM_SDCLK will internally rise at the mem_sdclk_phase+1st clk400 edge after internal changes of SDRAM signals (MEM_SD*-signals, MI address and data buses driven by clk_memsig) For correct settings delays depending on external capacitive load have to be respected. Note: The phase shift logic was op

Definition at line 15664 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::MR

[13..0] SDRAM Mode Register. CAS latency bits are typically located in MR[6:4]. Only CL2 and CL3 are supported, not CL1; default is CL3 Burst Length in MR[2:0] is read only here. Burst length depends on data bus width programmed in sdram_general_ctrl.dbus16 register bit The netX10 controller supports only Burst Length 8 (default) for 8bit SDRAM interface and 4 for 16bit SDRAM interface. Note: SDRAM devices where burst length is not located in Mode Register bits MR[2:0] are not supported by netX SDRAM controller. H

Definition at line 15713 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::refresh_mode

[25..24] Refresh request generation mode. Refresh behaviour changed from netx100/500/50: SDRAM controller now has an additional high priority refresh mode. Refresh generation has lower priority than accesses on external memory interface normally. That means refreshes do not block data access. To avoid data loss under all conditions without checking critical situations by software a high priority refresh mode is implemented for netX10 and later: If there was too much traffic to SDRAM to run refreshes according to pr

Definition at line 15593 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::refresh_status

[31..31] Refresh status flag. Refresh behaviour changed from netx100/500/50: SDRAM controller now has an additional high priority refresh mode (view refresh_mode bit description). There is no need to guarantee sufficient SDRAM refresh generation by checking this bit by software any longer (necessary for netx100/500/50 depending on application). It is only for information purpose for netX10 or later. This bit can be reset by writing '0' to it. Note: This bit is writable but can also be changed by hardware.

Definition at line 15609 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::rows

[5..4] Number of SDRAM device rows and address lines. 00 : 2k rows, address lines A0..A10 (default) 01 : 4k rows, address lines A0..A11 10 : 8k rows, address lines A0..A12

Definition at line 15563 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::sdram_general_ctrl

(@ 0x00000000) Control Register for external SDRAM access. For initializing procedure netX SDRAM controller view description of 'ctrl_en' bit inside this register. Note: This register can be protected by the register MODULE_FIREWALL_CTRL.firewall_cf _hifmemctrl.

Definition at line 15551 of file netx90_app.h.

struct { ... } hif_sdram_ctrl_Type::sdram_general_ctrl_b

__IOM uint32_t hif_sdram_ctrl_Type::sdram_mr

(@ 0x00000008) Mode Register for SDRAM device. Changes can only be done, if the SDRAM controller is disabled (sdram_general_ctrl.ctrl_en == 0) to avoid configuration problems. The SDRAM Mode Registers of the used SDRAM device will be set after enabling the SDRAM controller in the 200us SDRAM memory initialisation procedure. It is part of the SDRAM device and programmed by the LOAD MODE REGISTER command. For details of SDRAM Mode Register view datasheet of used SDRAM device. Please view description of 'ctrl

Definition at line 15699 of file netx90_app.h.

struct { ... } hif_sdram_ctrl_Type::sdram_mr_b

__IOM uint32_t hif_sdram_ctrl_Type::sdram_pwdn

[17..17] SDRAM power down If this bit is set, the controller will move SDRAM to power down self refresh mode (no data loss) and stop the external SDRAM clock. Return from power-down mode can be done by clearing this bit.

Definition at line 15576 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::sdram_ready

[30..30] SDRAM ready. This bit is set to 1 if SDRAM is ready for access. If sdram_general_ctrl.ctrl_en == 0 or sdram_general_ctrl.sdra _pwdn == 0 sdram_ready will be low. It will be set to 1 after SDRAM has been initialized or after power down wake up. Note: This bit is a read only status flag.

Definition at line 15604 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::sdram_timing_ctrl

(@ 0x00000004) Control Register for external SDRAM access. Changes can only be done, if the SDRAM controller is disabled (sdram_general_ctrl.ctrl_en == 0) to avoid configuration problems. Please view description of 'ctrl_en' bit inside sdram_general_ctrl register for initializing-procedure of netX SDRAM controller. Note: This register can be protected by the register MODULE_FIREWALL_CTRL.fire all_cfg_hifmemctrl. Note: For some registers the reset-value is a reserved value. I.e. these registers must be prog

Definition at line 15622 of file netx90_app.h.

struct { ... } hif_sdram_ctrl_Type::sdram_timing_ctrl_b

__IOM uint32_t hif_sdram_ctrl_Type::t_RAS

[10..8] ACTIVE to PRECHARGE command time (clk = t_RAS + 3) 000 : 3 clks 001 : 4 clks and so on 111 : 10 clks (default) Note: If Active-to-Active-command-period (t_RC) exceeds t_RAS+t_RP, set t_RAS and t_RP in a way that the following condition is met: t_RAS+t_RP>=t_RC.

Definition at line 15646 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::t_RCD

[1..0] ACTIVE to READ or WRITE time (RAS to CAS, clk = t_RCD) This value will be also taken as t_RRD (ACTIVE bank A to ACTIVE bank B time) 00 : 1 clk 01 : 2 clks 10 : 3 clks (default) 11 : reserved

Definition at line 15635 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::t_REFI

[17..16] Average periodic refresh interval (3.90 us * 2^t_REFI 00 : 3.90 us 01 : 7.80 us (default) 10 : 15.60 us 11 : 31.20 us Note: Typically refresh of SDRAM devices is specified by a certain number of refreshes that must be performed within a certain time. E.g. 8192 refreshes for 64ms. Dividing the time by the number of refreshes leads to the average periodic refresh interval. E.g. 64ms/8192 = 7.8us. Please view also description of 'refresh_mode' of 'sdram_general_ctrl' register for details.

Definition at line 15654 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::t_RFC

[15..12] REFRESH to next command time (clk = tRFC + 4) 0000 : 4 clks 0001 : 5 clks and so on 1111 : 19 clks (default)

Definition at line 15652 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::t_RP

[7..6] Precharge command period time (PRECHARGE to next command) 00 : 1 clk 01 : 2 clks 10 : 3 clks (default) 11 : reserved Note: For Active-to-Active-command-period (t_RC) view note at t_RAS.

Definition at line 15642 of file netx90_app.h.

__IOM uint32_t hif_sdram_ctrl_Type::t_WR

[5..4] Write recovery time (last write data to PRECHARGE) 00 : 1 clk 01 : 2 clks 10 : 3 clks (default) 11 : reserved

Definition at line 15640 of file netx90_app.h.

The documentation for this struct was generated from the following file:

netx90_app.h

Data Fields

Detailed Description

Field Documentation