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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
hash (hash) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __OM uint32_t hash_din | |
| struct { | |
| __OM uint32_t val: 32 | |
| } hash_din_b | |
| }; | |
| union { | |
| __IOM uint32_t hash_cfg | |
| struct { | |
| __IOM uint32_t mode: 3 | |
| __IOM uint32_t reset: 1 | |
| __IOM uint32_t dma_en: 1 | |
| __IOM uint32_t dma_burst_only: 1 | |
| __IOM uint32_t bf_align0: 26 | |
| } hash_cfg_b | |
| }; | |
| union { | |
| __IM uint32_t hash_stat | |
| struct { | |
| __IM uint32_t fifo_fill: 9 | |
| __IM uint32_t bf_align0: 23 | |
| } hash_stat_b | |
| }; | |
| union { | |
| __IM uint32_t hash_debug_info | |
| struct { | |
| __IM uint32_t sha_round: 7 | |
| __IM uint32_t bf_align0: 25 | |
| } hash_debug_info_b | |
| }; | |
| union { | |
| __IOM uint32_t hash_irq_raw | |
| struct { | |
| __IOM uint32_t hash_ready: 1 | |
| __IOM uint32_t fifo_underrun: 1 | |
| __IOM uint32_t fifo_overflow: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } hash_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t hash_irq_masked | |
| struct { | |
| __IM uint32_t hash_ready: 1 | |
| __IM uint32_t fifo_underrun: 1 | |
| __IM uint32_t fifo_overflow: 1 | |
| __IM uint32_t bf_align0: 29 | |
| } hash_irq_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t hash_irq_msk_set | |
| struct { | |
| __IOM uint32_t hash_ready: 1 | |
| __IOM uint32_t fifo_underrun: 1 | |
| __IOM uint32_t fifo_overflow: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } hash_irq_msk_set_b | |
| }; | |
| union { | |
| __IOM uint32_t hash_irq_msk_reset | |
| struct { | |
| __IOM uint32_t hash_ready: 1 | |
| __IOM uint32_t fifo_underrun: 1 | |
| __IOM uint32_t fifo_overflow: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } hash_irq_msk_reset_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout0 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout0_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout1 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout1_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout2 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout2_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout3 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout3_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout4 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout4_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout5 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout5_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout6 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout6_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout7 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout7_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout8 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout8_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout9 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout9_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout10 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout10_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout11 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout11_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout12 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout12_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout13 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout13_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout14 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout14_b | |
| }; | |
| union { | |
| __IM uint32_t hash_dout15 | |
| struct { | |
| __IM uint32_t val: 32 | |
| } hash_dout15_b | |
| }; | |
hash (hash)
Definition at line 2022 of file netx90_app.h.
| union { ... } |
< (@ 0xFF080000) hash Structure
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| union { ... } |
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| __IOM uint32_t hash_Type::bf_align0 |
[31..6] bitField alignment value for aeabi compatibility
[31..3] bitField alignment value for aeabi compatibility
Definition at line 2057 of file netx90_app.h.
| __IM uint32_t hash_Type::bf_align0 |
[31..9] bitField alignment value for aeabi compatibility
[31..7] bitField alignment value for aeabi compatibility
[31..3] bitField alignment value for aeabi compatibility
Definition at line 2066 of file netx90_app.h.
| __IOM uint32_t hash_Type::dma_burst_only |
[5..5] Generate DMAC burst signal only. When set to '1' the DMAC logic will only generate burst requests to the DMAC. This is to overcome limitations of the current DMA controller implementation that only accepts burst requests for DMAC controlled memory to peripheral transfers.
Definition at line 2052 of file netx90_app.h.
| __IOM uint32_t hash_Type::dma_en |
[4..4] Enable DMAC control signals
Definition at line 2051 of file netx90_app.h.
| __IM uint32_t hash_Type::fifo_fill |
[8..0] Fill level of FIFO in bytes (0..256)
Definition at line 2065 of file netx90_app.h.
| __IOM uint32_t hash_Type::fifo_overflow |
[2..2] input buffer was overflown, set hash_cfg-reset=1 to reset this bit.
[2..2] input buffer was overflown, set hash_cfg-reset=1 to reset this bit
Definition at line 2101 of file netx90_app.h.
| __IM uint32_t hash_Type::fifo_overflow |
[2..2] input buffer was overflown, set hash_cfg-reset=1 to reset this bit
Definition at line 2115 of file netx90_app.h.
| __IOM uint32_t hash_Type::fifo_underrun |
[1..1] input buffer was underrun, set hash_cfg-reset=1 to reset this bit. Note: underrun is only a theoretical FIFO status, because the hardware logic of the hash core won't fetch data from the FIFO when it's empty.
[1..1] input buffer was underrun, set hash_cfg-reset=1 to reset this bit
Definition at line 2097 of file netx90_app.h.
| __IM uint32_t hash_Type::fifo_underrun |
[1..1] input buffer was underrun, set hash_cfg-reset=1 to reset this bit
Definition at line 2113 of file netx90_app.h.
| __IOM uint32_t hash_Type::hash_cfg |
(@ 0x00000004) Hash config register:
Definition at line 2038 of file netx90_app.h.
| struct { ... } hash_Type::hash_cfg_b |
| __IM uint32_t hash_Type::hash_debug_info |
(@ 0x0000000C) Hash info register:
Definition at line 2071 of file netx90_app.h.
| struct { ... } hash_Type::hash_debug_info_b |
| __OM uint32_t hash_Type::hash_din |
(@ 0x00000000) Hash FIFO input: Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss. The FIFO controller will automatically collect data and start HASH-calculation, if enough data (complete DWords) are collected.
Definition at line 2025 of file netx90_app.h.
| struct { ... } hash_Type::hash_din_b |
| __IM uint32_t hash_Type::hash_dout0 |
(@ 0x00000020) Hash value0 register
Definition at line 2166 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout0_b |
| __IM uint32_t hash_Type::hash_dout1 |
(@ 0x00000024) Hash value1 register
Definition at line 2174 of file netx90_app.h.
| __IM uint32_t hash_Type::hash_dout10 |
(@ 0x00000048) Hash value10 register
Definition at line 2246 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout10_b |
| __IM uint32_t hash_Type::hash_dout11 |
(@ 0x0000004C) Hash value11 register
Definition at line 2254 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout11_b |
| __IM uint32_t hash_Type::hash_dout12 |
(@ 0x00000050) Hash value12 register
Definition at line 2262 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout12_b |
| __IM uint32_t hash_Type::hash_dout13 |
(@ 0x00000054) Hash value13 register
Definition at line 2270 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout13_b |
| __IM uint32_t hash_Type::hash_dout14 |
(@ 0x00000058) Hash value14 register
Definition at line 2278 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout14_b |
| __IM uint32_t hash_Type::hash_dout15 |
(@ 0x0000005C) Hash value15 register
Definition at line 2286 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout15_b |
| struct { ... } hash_Type::hash_dout1_b |
| __IM uint32_t hash_Type::hash_dout2 |
(@ 0x00000028) Hash value2 register
Definition at line 2182 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout2_b |
| __IM uint32_t hash_Type::hash_dout3 |
(@ 0x0000002C) Hash value3 register
Definition at line 2190 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout3_b |
| __IM uint32_t hash_Type::hash_dout4 |
(@ 0x00000030) Hash value4 register
Definition at line 2198 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout4_b |
| __IM uint32_t hash_Type::hash_dout5 |
(@ 0x00000034) Hash value5 register
Definition at line 2206 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout5_b |
| __IM uint32_t hash_Type::hash_dout6 |
(@ 0x00000038) Hash value6 register
Definition at line 2214 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout6_b |
| __IM uint32_t hash_Type::hash_dout7 |
(@ 0x0000003C) Hash value7 register
Definition at line 2222 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout7_b |
| __IM uint32_t hash_Type::hash_dout8 |
(@ 0x00000040) Hash value8 register
Definition at line 2230 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout8_b |
| __IM uint32_t hash_Type::hash_dout9 |
(@ 0x00000044) Hash value9 register
Definition at line 2238 of file netx90_app.h.
| struct { ... } hash_Type::hash_dout9_b |
| __IM uint32_t hash_Type::hash_irq_masked |
(@ 0x00000014) Hash masked IRQ: Shows status of masked IRQs.
Definition at line 2108 of file netx90_app.h.
| struct { ... } hash_Type::hash_irq_masked_b |
| __IOM uint32_t hash_Type::hash_irq_msk_reset |
(@ 0x0000001C) Hash IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 2146 of file netx90_app.h.
| struct { ... } hash_Type::hash_irq_msk_reset_b |
| __IOM uint32_t hash_Type::hash_irq_msk_set |
(@ 0x00000018) Hash IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to crypt_hash_irq_raw.
Definition at line 2122 of file netx90_app.h.
| struct { ... } hash_Type::hash_irq_msk_set_b |
| __IOM uint32_t hash_Type::hash_irq_raw |
(@ 0x00000010) Hash raw IRQ: Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ. Write access with '0' does not influence this bit.
Definition at line 2080 of file netx90_app.h.
| struct { ... } hash_Type::hash_irq_raw_b |
| __IOM uint32_t hash_Type::hash_ready |
[0..0] Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid. Note: This interrupt will be asserted when the hash FIFO is empty and the calculation of the last block from the FIFO has finished. The interrupt will be re-asserted after clearing as long as no new data has been fed into the FIFO or a software reset has been performed (hash_cfg-reset=1). Note: This interrupt could have got asserted in situations where the FIFO runs empty, the hash core finished the operation
[0..0] Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid
Definition at line 2088 of file netx90_app.h.
| __IM uint32_t hash_Type::hash_ready |
[0..0] Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid
Definition at line 2111 of file netx90_app.h.
| __IM uint32_t hash_Type::hash_stat |
(@ 0x00000008) Hash status register:
Definition at line 2062 of file netx90_app.h.
| struct { ... } hash_Type::hash_stat_b |
| __IOM uint32_t hash_Type::mode |
[2..0] Hash core mode 101: MD5 100: SHA2-512 011: SHA2-384 010: SHA2-256 001: SHA2-224 000: SHA1-160 Note: When changing the mode, a reset must be performed to correctly initialize the SHA/MD5 core. This can be done by setting the 'reset' bit together with the new mode or in a second access after setting the mode.
Definition at line 2041 of file netx90_app.h.
| __IOM uint32_t hash_Type::reset |
[3..3] Reset of SHA engine: After writing '1', this bit will automatically be reset. 1: reset internal registers, use this to start calculation of new hash 0: start calculation as soon as enough data in FIFO buffer
Definition at line 2047 of file netx90_app.h.
| __IM uint32_t hash_Type::sha_round |
[6..0] 7bit current state counter of the SHA core.
Definition at line 2074 of file netx90_app.h.
| __OM uint32_t hash_Type::val |
[31..0] data bits
Definition at line 2033 of file netx90_app.h.
| __IM uint32_t hash_Type::val |
[31..0] data bits 31..0
[31..0] data bits 63..32
[31..0] data bits 95..64
[31..0] data bits 127..96
[31..0] data bits 159..128
[31..0] data bits 191..160
[31..0] data bits 223..192
[31..0] data bits 255..224
[31..0] data bits 287..256
[31..0] data bits 319..288
[31..0] data bits 351..320
[31..0] data bits 383..352
[31..0] data bits 415..384
[31..0] data bits 447..416
[31..0] data bits 479..448
[31..0] data bits 511..480
Definition at line 2169 of file netx90_app.h.
1.8.11