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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
gpio_xpic_app (gpio_xpic_app) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IOM uint32_t gpio_app_cfg [8] | |
| struct { | |
| __IOM uint32_t mode: 4 | |
| __IOM uint32_t inv: 1 | |
| __IOM uint32_t count_ref: 2 | |
| __IOM uint32_t blink_len: 5 | |
| __IOM uint32_t blink_once: 1 | |
| __IOM uint32_t bf_align0: 19 | |
| } gpio_app_cfg_b [8] | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_tc [8] | |
| struct { | |
| __IOM uint32_t val: 32 | |
| } gpio_app_tc_b [8] | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_counter_ctrl [3] | |
| struct { | |
| __IOM uint32_t run: 1 | |
| __IOM uint32_t sym_nasym: 1 | |
| __IOM uint32_t irq_en: 1 | |
| __IOM uint32_t sel_event: 1 | |
| __IOM uint32_t once: 1 | |
| __IOM uint32_t event_act: 2 | |
| __IOM uint32_t gpio_ref: 3 | |
| __IOM uint32_t bf_align0: 22 | |
| } gpio_app_counter_ctrl_b [3] | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_counter_max [3] | |
| struct { | |
| __IOM uint32_t val: 32 | |
| } gpio_app_counter_max_b [3] | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_counter_cnt [3] | |
| struct { | |
| __IOM uint32_t val: 32 | |
| } gpio_app_counter_cnt_b [3] | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_line | |
| struct { | |
| __IOM uint32_t val: 8 | |
| __IOM uint32_t bf_align0: 24 | |
| } gpio_app_line_b | |
| }; | |
| union { | |
| __IM uint32_t gpio_app_in | |
| struct { | |
| __IM uint32_t val: 8 | |
| __IM uint32_t bf_align0: 24 | |
| } gpio_app_in_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_irq_raw | |
| struct { | |
| __IOM uint32_t gpio_app0: 1 | |
| __IOM uint32_t gpio_app1: 1 | |
| __IOM uint32_t gpio_app2: 1 | |
| __IOM uint32_t gpio_app3: 1 | |
| __IOM uint32_t gpio_app4: 1 | |
| __IOM uint32_t gpio_app5: 1 | |
| __IOM uint32_t gpio_app6: 1 | |
| __IOM uint32_t gpio_app7: 1 | |
| __IOM uint32_t bf_align0: 24 | |
| } gpio_app_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t gpio_app_irq_masked | |
| struct { | |
| __IM uint32_t gpio_app0: 1 | |
| __IM uint32_t gpio_app1: 1 | |
| __IM uint32_t gpio_app2: 1 | |
| __IM uint32_t gpio_app3: 1 | |
| __IM uint32_t gpio_app4: 1 | |
| __IM uint32_t gpio_app5: 1 | |
| __IM uint32_t gpio_app6: 1 | |
| __IM uint32_t gpio_app7: 1 | |
| __IM uint32_t bf_align0: 24 | |
| } gpio_app_irq_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_irq_mask_set | |
| struct { | |
| __IOM uint32_t gpio_app0: 1 | |
| __IOM uint32_t gpio_app1: 1 | |
| __IOM uint32_t gpio_app2: 1 | |
| __IOM uint32_t gpio_app3: 1 | |
| __IOM uint32_t gpio_app4: 1 | |
| __IOM uint32_t gpio_app5: 1 | |
| __IOM uint32_t gpio_app6: 1 | |
| __IOM uint32_t gpio_app7: 1 | |
| __IOM uint32_t bf_align0: 24 | |
| } gpio_app_irq_mask_set_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_irq_mask_rst | |
| struct { | |
| __IOM uint32_t gpio_app0: 1 | |
| __IOM uint32_t gpio_app1: 1 | |
| __IOM uint32_t gpio_app2: 1 | |
| __IOM uint32_t gpio_app3: 1 | |
| __IOM uint32_t gpio_app4: 1 | |
| __IOM uint32_t gpio_app5: 1 | |
| __IOM uint32_t gpio_app6: 1 | |
| __IOM uint32_t gpio_app7: 1 | |
| __IOM uint32_t bf_align0: 24 | |
| } gpio_app_irq_mask_rst_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_cnt_irq_raw | |
| struct { | |
| __IOM uint32_t cnt0: 1 | |
| __IOM uint32_t cnt1: 1 | |
| __IOM uint32_t cnt2: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } gpio_app_cnt_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t gpio_app_cnt_irq_masked | |
| struct { | |
| __IM uint32_t cnt0: 1 | |
| __IM uint32_t cnt1: 1 | |
| __IM uint32_t cnt2: 1 | |
| __IM uint32_t bf_align0: 29 | |
| } gpio_app_cnt_irq_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_cnt_irq_mask_set | |
| struct { | |
| __IOM uint32_t cnt0: 1 | |
| __IOM uint32_t cnt1: 1 | |
| __IOM uint32_t cnt2: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } gpio_app_cnt_irq_mask_set_b | |
| }; | |
| union { | |
| __IOM uint32_t gpio_app_cnt_irq_mask_rst | |
| struct { | |
| __IOM uint32_t cnt0: 1 | |
| __IOM uint32_t cnt1: 1 | |
| __IOM uint32_t cnt2: 1 | |
| __IOM uint32_t bf_align0: 29 | |
| } gpio_app_cnt_irq_mask_rst_b | |
| }; | |
gpio_xpic_app (gpio_xpic_app)
Definition at line 31625 of file netx90_app.h.
| union { ... } |
< (@ 0xFF900200) gpio_xpic_app Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IOM uint32_t gpio_xpic_app_Type::bf_align0 |
[31..13] bitField alignment value for aeabi compatibility
[31..10] bitField alignment value for aeabi compatibility
[31..8] bitField alignment value for aeabi compatibility
[31..3] bitField alignment value for aeabi compatibility
Definition at line 31650 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::bf_align0 |
[31..8] bitField alignment value for aeabi compatibility
[31..3] bitField alignment value for aeabi compatibility
Definition at line 31738 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::blink_len |
[11..7] Length of blink sequence minus 1 (blink mode only) 00000: use bit 0 of gpio_app_tc 00001: use bits 0..1 of gpio_app_tc 00010: use bits 0..2 of gpio_app_tc ... 11111: use bits 0..31 of gpio_app_tc
Definition at line 31645 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::blink_once |
[12..12] Run blink sequence only once (blink mode only)
Definition at line 31649 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::cnt0 |
[0..0] Interrupt bit for counter0
Definition at line 31848 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::cnt0 |
[0..0] Interrupt bit for counter0
Definition at line 31865 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::cnt1 |
[1..1] Interrupt bit for counter1
Definition at line 31849 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::cnt1 |
[1..1] Interrupt bit for counter1
Definition at line 31866 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::cnt2 |
[2..2] Interrupt bit for counter2
Definition at line 31850 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::cnt2 |
[2..2] Interrupt bit for counter2
Definition at line 31867 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::count_ref |
[6..5] counter reference 00: counter 0 01: counter 1 10: counter 2 11: sys_time (global system time)
Definition at line 31643 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::event_act |
[6..5] Define action of selected external event (dependent on sel_event, gpio_ref) 00: count every clock cycle, ignore external events 01: count only external events (edge or level according to bit sel_event) 10: enable watchdog mode of counter (external event will be reset without IRQ, overflow generates IRQ). 11: enable automatic run mode (external event sets run bit, used for DC-DC PWM in combination with bit once=1)
Definition at line 31687 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app0 |
[0..0] Interrupt bit for GPIO_APP0
Definition at line 31753 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app0 |
[0..0] Interrupt bit for GPIO_APP0
Definition at line 31773 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app1 |
[1..1] Interrupt bit for GPIO_APP1
Definition at line 31754 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app1 |
[1..1] Interrupt bit for GPIO_APP1
Definition at line 31774 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app2 |
[2..2] Interrupt bit for GPIO_APP2
Definition at line 31755 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app2 |
[2..2] Interrupt bit for GPIO_APP2
Definition at line 31775 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app3 |
[3..3] Interrupt bit for GPIO_APP3
Definition at line 31756 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app3 |
[3..3] Interrupt bit for GPIO_APP3
Definition at line 31776 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app4 |
[4..4] Interrupt bit for GPIO_APP4
Definition at line 31757 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app4 |
[4..4] Interrupt bit for GPIO_APP4
Definition at line 31777 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app5 |
[5..5] Interrupt bit for GPIO_APP5
Definition at line 31758 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app5 |
[5..5] Interrupt bit for GPIO_APP5
Definition at line 31778 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app6 |
[6..6] Interrupt bit for GPIO_APP6
Definition at line 31759 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app6 |
[6..6] Interrupt bit for GPIO_APP6
Definition at line 31779 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app7 |
[7..7] Interrupt bit for GPIO_APP7
Definition at line 31760 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::gpio_app7 |
[7..7] Interrupt bit for GPIO_APP7
Definition at line 31780 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_cfg[8] |
(@ 0x00000000) GPIO_APP pin 0 config register: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31628 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_cfg_b[8] |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_cnt_irq_mask_rst |
(@ 0x00000088) Counter interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources. Like cnt_irq_msk_set, this address exists for the following address areas: inlogic_app, xpic_app_system. Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source). Write access with '0' does not influence this bit. Read access shows the current interrupt mask.
Definition at line 31895 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_cnt_irq_mask_rst_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_cnt_irq_mask_set |
(@ 0x00000084) Counter interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP. The inlogic_app IRQ mask enables interrupt requests for ARM_APP. The xpic_app_system IRQ mask enables interrupt requests for xPIC_APP. Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks: Write access wi
Definition at line 31873 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_cnt_irq_mask_set_b |
| __IM uint32_t gpio_xpic_app_Type::gpio_app_cnt_irq_masked |
(@ 0x00000080) Counter masked IRQ register: Read access shows the status of masked IRQs (cnt_irq_raw AND cnt_irq_mask). This register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
Definition at line 31856 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_cnt_irq_masked_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_cnt_irq_raw |
(@ 0x0000007C) Counter raw IRQ register: Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the corresponding IRQ. Write access with '0' does not influence this bit. This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31839 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_cnt_irq_raw_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_counter_cnt[3] |
(@ 0x00000058) GPIO_APP counter0 current value: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31712 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_counter_cnt_b[3] |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_counter_ctrl[3] |
(@ 0x00000040) GPIO_APP counter0 control register: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31673 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_counter_ctrl_b[3] |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_counter_max[3] |
(@ 0x0000004C) GPIO_APP counter0 max value: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31701 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_counter_max_b[3] |
| __IM uint32_t gpio_xpic_app_Type::gpio_app_in |
(@ 0x00000068) GPIO_APP latched inputs register: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31732 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_in_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_irq_mask_rst |
(@ 0x00000078) GPIO_APP interrupt mask reset: This reset mask serves to disable the interrupt requests for the corresponding interrupt sources. Like irq_msk_set, this address exists for the following address areas: inlogic_app, xpic_app_system. Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source). Write access with '0' does not influence this bit. Read access shows the current interrupt mask.
Definition at line 31813 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_irq_mask_rst_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_irq_mask_set |
(@ 0x00000074) GPIO_APP interrupt mask set: The interrupt mask register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP. The inlogic_app IRQ mask enables interrupt requests for ARM_APP. The xpic_app_system IRQ mask enables interrupt requests for xPIC_APP. Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks: Write access w
Definition at line 31786 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_irq_mask_set_b |
| __IM uint32_t gpio_xpic_app_Type::gpio_app_irq_masked |
(@ 0x00000070) GPIO_APP masked IRQ register: This register exists 2x for the different system busses (address areas) it is connected to. This allows 2 CPUs to work in parallel on this module: ARM_APP, xPIC_APP.
Definition at line 31766 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_irq_masked_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_irq_raw |
(@ 0x0000006C) GPIO_APP raw IRQ register: Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the corresponding IRQ. Write access with '0' does not influence this bit. This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31743 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_irq_raw_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_line |
(@ 0x00000064) GPIO_APP line register This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31722 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_line_b |
| __IOM uint32_t gpio_xpic_app_Type::gpio_app_tc[8] |
(@ 0x00000020) GPIO_APP pin 0 threshold or capture register: This register is accessible via address areas inlogic_app and xpic_app_system.
Definition at line 31655 of file netx90_app.h.
| struct { ... } gpio_xpic_app_Type::gpio_app_tc_b[8] |
| __IOM uint32_t gpio_xpic_app_Type::gpio_ref |
[9..7] gpio reference (0 - 7)
Definition at line 31695 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::inv |
[4..4] 1: invert input/output value 0: do not invert input/output
Definition at line 31642 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::irq_en |
[2..2] 1: enable interrupt request on sel_event 0: disable interrupt request
Definition at line 31680 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::mode |
[3..0] defines the gp input or output mode - depends on io_cfg Input modes: 0000: read mode 0001: capture continued at rising edge (allows gpio_app_irq on each capture) 0010: capture once at rising edge (reset gpio_app_irq to capture again) 0011: capture once at high level (reset gpio_app_irq to capture again) Output modes: 0100: set to 0 0101: set to 1 0110: set to gpio_app_line[0] 0111: pwm mode, direct threshold update (might cause hazards on output) 1000: blink mode Multi pin modes: 1111: pwm2-mode with thres
Definition at line 31633 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::once |
[4..4] 1: count once (reset run bit after 1 period) 0: count continuously
Definition at line 31685 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::run |
[0..0] 1: start counter, counter is running 0: stop counter
Definition at line 31678 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::sel_event |
[3..3] select external event 0: high level, invert gpio in register gpio_app_cfg to select low level 1: pos. edge, invert gpio in register gpio_app_cfg to select neg. edge
Definition at line 31682 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::sym_nasym |
[1..1] 1: symmetric mode (triangle) 0: asymmetric mode (sawtooth)
Definition at line 31679 of file netx90_app.h.
| __IOM uint32_t gpio_xpic_app_Type::val |
[31..0] Threshold/Capture register: PWM mode (threshold): { | The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0). Therefore it is interpreted differently in symmetrical and asymmetrical counter mode: Asymmetrical mode (sawtooth): pwm = (counter >= gpio_app_tc) Symmetrical mode (triangle) : Counter is compared with gpio_app_tc[31:1], gpio_app_tc[0] extends the inactive phase by 1 clock cycle only while counting up. This allows running a 10 ns resolution even in sym
[31..0] Asymmetric mode: Counting period in cc + 1 Symmetric mode: Counting period in cc
[31..0] current counter value
[7..0] gpio_app output values
Definition at line 31660 of file netx90_app.h.
| __IM uint32_t gpio_xpic_app_Type::val |
[7..0] gpio_app input values
Definition at line 31737 of file netx90_app.h.
1.8.11