endat1_app (endat1_app) More...

#include <netx90_app.h>

Collaboration diagram for endat1_app_Type:

Data Fields
union {
__IOM uint32_t endat_send

struct {
__IOM uint32_t byte1: 8

__IOM uint32_t byte2: 8

__IOM uint32_t byte3: 8

__IOM uint32_t byte4: 6

__IOM uint32_t bf_align0: 2

} endat_send_b

};

union {
__IM uint32_t endat_receive1_0

struct {
__IM uint32_t byte1: 8

__IM uint32_t byte2: 8

__IM uint32_t byte3: 8

__IM uint32_t byte4: 8

} endat_receive1_0_b

};

union {
__IM uint32_t endat_receive1_1

struct {
__IM uint32_t byte5: 8

__IM uint32_t byte6: 8

__IM uint32_t byte7: 8

__IM uint32_t bf_align0: 8

} endat_receive1_1_b

};

union {
__IM uint32_t endat_receive2

struct {
__IM uint32_t byte1: 8

__IM uint32_t byte2: 8

__IM uint32_t byte3: 8

__IM uint32_t byte4: 8

} endat_receive2_b

};

union {
__IM uint32_t endat_receive3

struct {
__IM uint32_t byte1: 8

__IM uint32_t byte2: 8

__IM uint32_t byte3: 8

__IM uint32_t byte4: 8

} endat_receive3_b

};

union {
__IOM uint32_t endat_conf1

struct {
__IOM uint32_t hw_strobe: 1

__IOM uint32_t uncond_transfer: 1

__IOM uint32_t endat_cont_clk_mode: 1

__IOM uint32_t bf_align0: 1

__IOM uint32_t f_tclk: 4

__IOM uint32_t data_word_len: 6

__IOM uint32_t reset_window: 1

__IOM uint32_t auto_reset: 1

__IOM uint32_t cable_prop_time: 8

__IOM uint32_t delay_comp: 1

__IOM uint32_t bf_align1: 1

__IOM uint32_t f_sys: 3

__IOM uint32_t ic_reset: 1

__IOM uint32_t endat_ssi: 2

} endat_conf1_b

};

union {
__IOM uint32_t endat_conf2

struct {
__IOM uint32_t timer_for_sampling_rate: 8

__IOM uint32_t watchdog: 8

__IOM uint32_t t_st: 3

__IOM uint32_t filter: 3

__IOM uint32_t rtm: 1

__IOM uint32_t bf_align0: 1

__IOM uint32_t hw_strobe_delay: 8

} endat_conf2_b

};

union {
__IOM uint32_t endat_conf3

struct {
__IOM uint32_t parity: 1

__IOM uint32_t format: 1

__IOM uint32_t gray_to_binary: 1

__IOM uint32_t singleturn_res: 5

__IOM uint32_t dw: 1

__IOM uint32_t bf_align0: 6

__IOM uint32_t speed: 1

__IOM uint32_t bf_align1: 16

} endat_conf3_b

};

union {
__IOM uint32_t endat_stat

struct {
__IOM uint32_t receive1_reg: 1

__IOM uint32_t error1: 1

__IOM uint32_t crcpw_parity: 1

__IOM uint32_t f_type1: 1

__IOM uint32_t f_type2: 1

__IOM uint32_t mrs_adr: 1

__IOM uint32_t ir6: 1

__IOM uint32_t ir7: 1

__IOM uint32_t receive2_reg: 1

__IOM uint32_t receive3_reg: 1

__IOM uint32_t error2: 1

__IOM uint32_t crc_zi1: 1

__IOM uint32_t crc_zi2: 1

__IOM uint32_t busy: 1

__IOM uint32_t rm: 1

__IOM uint32_t wrn: 1

__IOM uint32_t spike: 1

__IOM uint32_t watchdog: 1

__IOM uint32_t f_type3: 1

__IOM uint32_t bf_align0: 3

__IOM uint32_t delay_comp: 1

__IOM uint32_t prop_time_measurement: 1

__IOM uint32_t bf_align1: 3

__IOM uint32_t rtm_start: 1

__IOM uint32_t rtm_stop: 1

__IOM uint32_t speed_ready: 1

__IOM uint32_t ready_for_strobe: 1

__IOM uint32_t ready: 1

} endat_stat_b

};

union {
__IOM uint32_t endat_int

struct {
__IOM uint32_t receive1_reg: 1

__IOM uint32_t error1: 1

__IOM uint32_t crcpw_parity: 1

__IOM uint32_t f_type1: 1

__IOM uint32_t f_type2: 1

__IOM uint32_t mrs_adr: 1

__IOM uint32_t ir6: 1

__IOM uint32_t ir7: 1

__IOM uint32_t receive2_reg: 1

__IOM uint32_t receive3_reg: 1

__IOM uint32_t error2: 1

__IOM uint32_t crc_zi1: 1

__IOM uint32_t crc_zi2: 1

__IOM uint32_t busy: 1

__IOM uint32_t RM: 1

__IOM uint32_t wrn: 1

__IOM uint32_t spike: 1

__IOM uint32_t watchdog: 1

__IOM uint32_t f_type3: 1

__IOM uint32_t bf_align0: 10

__IOM uint32_t speed_ready: 1

__IOM uint32_t bf_align1: 1

__IOM uint32_t ready: 1

} endat_int_b

};

union {
__IM uint32_t endat_test1

struct {
__IM uint32_t dl_high: 1

__IM uint32_t status_zi: 2

__IM uint32_t bf_align0: 1

__IM uint32_t enDat_automation_engine: 6

__IM uint32_t ic_test_values: 22

} endat_test1_b

};

union {
__IOM uint32_t endat_test2

struct {
__IOM uint32_t bf_align0: 2

__IOM uint32_t selection_tst_out: 1

__IOM uint32_t test_receive_reg: 1

__IOM uint32_t sel_test_mux: 2

__IOM uint32_t bf_align1: 1

__IOM uint32_t ic_test_mode: 1

__IOM uint32_t selection_add_info: 3

__IOM uint32_t test_mode_divider: 1

__IOM uint32_t sel_test_mux2: 2

__IOM uint32_t sel_test_mux3: 2

__IOM uint32_t ic_test_data: 16

} endat_test2_b

};

union {
__IM uint32_t endat_receive4_0

struct {
__IM uint32_t byte1: 8

__IM uint32_t byte2: 8

__IM uint32_t byte3: 8

__IM uint32_t byte4: 8

} endat_receive4_0_b

};

union {
__IM uint32_t endat_receive4_1

struct {
__IM uint32_t byte5: 8

__IM uint32_t byte6: 8

__IM uint32_t bf_align0: 16

} endat_receive4_1_b

};

union {
__OM uint32_t endat_sw_strobe

struct {
__OM uint32_t sw_strobe: 32

} endat_sw_strobe_b

};

union {
__IM uint32_t endat_id

struct {
__IM uint32_t id: 32

} endat_id_b

};

Detailed Description

endat1_app (endat1_app)

Definition at line 26550 of file netx90_app.h.

Field Documentation

union { ... }

< (@ 0xFF802040) endat1_app Structure

union { ... }

__IOM uint32_t endat1_app_Type::auto_reset

[15..15] Autom. reset (automatic reset). If this bit is set, resetting of the status register and error register is performed automatically Autom. reset = 0 Resetting of the above-mentioned registers must be performed by the application. Autom. reset = 1 Resetting of the above-mentioned registers is done automatically. However, this resetting only occurs in the next EnDat transmission with the start of data reception. For safety applications: autom. reset = 0

Definition at line 26667 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::bf_align0

[31..30] bitField alignment value for aeabi compatibility

[3..3] bitField alignment value for aeabi compatibility

[23..23] bitField alignment value for aeabi compatibility

[14..9] bitField alignment value for aeabi compatibility

[21..19] bitField alignment value for aeabi compatibility

[28..19] bitField alignment value for aeabi compatibility

[1..0] bitField alignment value for aeabi compatibility

Definition at line 26564 of file netx90_app.h.

__IM uint32_t endat1_app_Type::bf_align0

[31..24] bitField alignment value for aeabi compatibility

[3..3] bitField alignment value for aeabi compatibility

[31..16] bitField alignment value for aeabi compatibility

Definition at line 26591 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::bf_align1

[25..25] bitField alignment value for aeabi compatibility

[31..16] bitField alignment value for aeabi compatibility

[26..24] bitField alignment value for aeabi compatibility

[30..30] bitField alignment value for aeabi compatibility

[6..6] bitField alignment value for aeabi compatibility

Definition at line 26692 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::busy

[13..13] Contains the Busy status bit as transmitted in the EnDat protocol. Busy = 0 Busy = 1

[13..13] ...

Definition at line 26838 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::byte1

[7..0] Parameters / Instructions D[7:0]

Definition at line 26560 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte1

[7..0] ...

Definition at line 26577 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::byte2

[15..8] Parameters / Instructions D[15:0]

Definition at line 26561 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte2

[15..8] ...

Definition at line 26578 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::byte3

[23..16] MRS code / Address / Port address A[7:0]

Definition at line 26562 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte3

[23..16] ...

Definition at line 26579 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::byte4

[29..24] Mode bits M[5:0]

Definition at line 26563 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte4

[31..24] ...

Definition at line 26580 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte5

[7..0] ...

Definition at line 26588 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte6

[15..8] ...

Definition at line 26589 of file netx90_app.h.

__IM uint32_t endat1_app_Type::byte7

[23..16] ...

Definition at line 26590 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::cable_prop_time

[23..16] The cable propagation time determined by the interface component is stored here. (The application may change this value. If that is the case the status registers propagation time measurement (LZM) bit will automatically be reset). The binary value has a step width of one system clock. At a system clock of 64 MHz, this corresponds to a setting range from 0 us to 3.98 us in steps of 15.6 ns. The basic setting is 00 hex

Definition at line 26675 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::crc_zi1

[11..11] During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI1). CRC check of ZI2 okay = 0 CRC check of ZI2 faulty = 1

[11..11] ...

Definition at line 26832 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::crc_zi2

[12..12] During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI2). CRC check of ZI2 okay = 0 CRC check of ZI2 faulty = 1

[12..12] ...

Definition at line 26835 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::crcpw_parity

[2..2] This bit has two meanings. With EnDat transmission it represents the result of the CRC check of the received value (position value, parameter or test value). With SSI transmission it shows the result of the parity check. Condition: parity check in conf-Reg1 is switched on. CRC check or parity check okay = 0 CRC and parity check faulty = 1

[2..2] ...

Definition at line 26792 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::data_word_len

[13..8] Here the data word length is set binary with 6 bits for EnDat or SSI. The permissible setting range for EnDat is from 8 bits to 48 bits. The permissible setting range for SSI is from 8 bits to 48 bits. Data word length = 0 bits = 00 1000 : Data word length = 13 bits = 00 1101 : Data word length = 48 bits = 11 0000 Note: The Data word length has to set to 40/d bit while using mode command 'encoder transmit test values'. Note: In SSI mode the additionally required clock cycle for the parity bit is generated

Definition at line 26650 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::delay_comp

[24..24] Delay compensation. This bit switches propagation delay compensation on. When this bit is set, propagation time measurement is performed with the next data transmission to the EnDat encoder. The interface component determines the cable propagation time and saves this in conf_reg1. This value is used to determine propagation delay compensation. To measure the propagation time again, the delay compensation bit must be reset and set again. For 16-bit access it must be considered that the measured cable propag

[22..22] (LZK). This bit reports if propagation delay compensation is active. If propagation delay compensation in configuration register 1 is switched off, this bit and propagation time measurement will automatically be reset. LZK inactive = 0 LZK active = 1 Neither the LZM nor the LZK bit can be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines. Neither of the two bits can cause an interrupt.

Definition at line 26683 of file netx90_app.h.

__IM uint32_t endat1_app_Type::dl_high

[0..0] For control of the EnDat automation machine.

Definition at line 26941 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::dw

[8..8] This bit allows a double-word query to be selected with SSI transmission. Double-word query off = 0 Double word query on = 1

Definition at line 26759 of file netx90_app.h.

__IM uint32_t endat1_app_Type::enDat_automation_engine

[9..4] ...

Definition at line 26949 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::endat_conf1

(@ 0x00000014) Configuration register 1

Definition at line 26629 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_conf1_b

__IOM uint32_t endat1_app_Type::endat_conf2

(@ 0x00000018) Configuration register 2

Definition at line 26707 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_conf2_b

__IOM uint32_t endat1_app_Type::endat_conf3

(@ 0x0000001C) Configuration register 3

Definition at line 26746 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_conf3_b

__IOM uint32_t endat1_app_Type::endat_cont_clk_mode

[2..2] This bit is used to select the EnDat continuous clock mode. Continuous clock off = 0 Continuous clock on = 1

Definition at line 26640 of file netx90_app.h.

__IM uint32_t endat1_app_Type::endat_id

(@ 0x0000003C) Identification register The soft-macro specification (ID) is stored here. This information is helpful for automated configuration by higher-level user software. E22: Designates the latest EnDat 2.2 protocol generation 6: MAZeT-internal designation (E6) xxxx: Consecutive version number (this document is valid for all versions as of xx13.)

Definition at line 27050 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_id_b

__IOM uint32_t endat1_app_Type::endat_int

(@ 0x00000024) Interrupt mask The interrupt mask register is for the masking of the status registers interrupt sources. All bits shown in the status register (except for LZM, LZK, Ready for Strobe) can generate an interrupt. The bit assignments of the interrupt mask register are identical to those of the status register. An interrupt is allowed by setting the corresponding bit to 1. The INT output changes from three-state to low.

Definition at line 26899 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_int_b

__IM uint32_t endat1_app_Type::endat_receive1_0

(@ 0x00000004) Receive register 1 Depending on the transmitted type 2.1 mode command, receive register 1 contains different data. With EnDat type 2.2 mode commands and with SSI, the position value is always entered into receive-Reg

Definition at line 26569 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive1_0_b

__IM uint32_t endat1_app_Type::endat_receive1_1

(@ 0x00000008) Receive register 1

Definition at line 26585 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive1_1_b

__IM uint32_t endat1_app_Type::endat_receive2

(@ 0x0000000C) Receive register 2 If a type 2.2 mode command was sent, receive register 2 will contain the contents of additional information 2 and its CRC. This data is to be interpreted in accordance with the EnDat Interface Description. In SSI protocol mode with double-word transmission, the redundant position value is stored here (right-aligned).

Definition at line 26596 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive2_b

__IM uint32_t endat1_app_Type::endat_receive3

(@ 0x00000010) Receive register 3 If a type 2.2 mode command was sent, receive register 3 will contain the contents of additional information 1 and its CRC. This data is to be interpreted in accordance with the EnDat Interface Description.

Definition at line 26614 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive3_b

__IM uint32_t endat1_app_Type::endat_receive4_0

(@ 0x00000030) Receive register 4 Receive register 4 contains position value 2 (Pos2), which is put together from the additional information 1 of Cycles 2, 3 and 4. Test function: with the test register 2 bits (13:12), internal test values can be read

Definition at line 27015 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive4_0_b

__IM uint32_t endat1_app_Type::endat_receive4_1

(@ 0x00000034) Receive register 4

Definition at line 27031 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_receive4_1_b

__IOM uint32_t endat1_app_Type::endat_send

(@ 0x00000000) Send register The send register contains data to be transmitted to the EnDat encoder. Mode command MRS code/address/port address (depends on the mode command) Parameters/instructions (depends on the mode command)

Definition at line 26553 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_send_b

__IOM uint32_t endat1_app_Type::endat_ssi

[31..30] These two bits set either the EnDat (0x2) or the SSI (0x1) transmission mode. Values 0x0 and 0x3 are not permitted. Note: For debugging purposes, this function may also be used to perform an internal status engine software reset without clearing of the other internal registers.

Definition at line 26698 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::endat_stat

(@ 0x00000020) Status register The status bits are created by the sequencing controller of the interface component, as required. Status information remains set until it is reset by the application. The application can selectively reset status information with a write command. This occurs by writing 1 to the selected bits. In the event of concurrent access, the internal sequencing controller has priority. This ensures that status information is not 'lost'. The status bits (15:11) are only valid when additio

Definition at line 26770 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_stat_b

__OM uint32_t endat1_app_Type::endat_sw_strobe

(@ 0x00000038) SW strobe

Definition at line 27041 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_sw_strobe_b

__IM uint32_t endat1_app_Type::endat_test1

(@ 0x00000028) Test register 1

Definition at line 26938 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_test1_b

__IOM uint32_t endat1_app_Type::endat_test2

(@ 0x0000002C) Test register 2

Definition at line 26955 of file netx90_app.h.

struct { ... } endat1_app_Type::endat_test2_b

__IOM uint32_t endat1_app_Type::error1

[1..1] The status bit error1 from the EnDat protocol is entered here. Error1 did not occur = 0 Error1 occurred = 1

[1..1] ...

Definition at line 26790 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::error2

[10..10] Contains the /Error 2 status bit from the EnDat protocol (only with EnDat2.2 commands). /Error2 occurred = 0 /Error2 did not occur = 1

[10..10] ...

Definition at line 26829 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::f_sys

[28..26] The system frequency actually used must be selected here. 64/48/32/50/100 MHz = 000/010/100/101/110

Definition at line 26693 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::f_tclk

[7..4] Setting (4 bit) of transmission rate for EnDat and SSI from 100 kHz to 1 MHz (SSI) or 16 MHz (EnDat). Transmission frequency = 100kHz = 1111 Transmission frequency = 200kHz = 1110 Transmission frequency = 1MHz = 1101 Transmission frequency = 2MHz = 1100 Transmission frequency = 4.16MHz = 1011 Transmission frequency = 8.33MHz = 0110 Transmission frequency = 16.67MHz = 0000..0011

Definition at line 26643 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::f_type1

[3..3] Shows type I error handling in accordance with the EnDat specification at Annex A2. A type I error did not occur = 0 A type I error occurred = 1

[3..3] ...

Definition at line 26798 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::f_type2

[4..4] Shows type II error handling in accordance with the EnDat specification at Annex A2. A type II error did not occur = 0 A type II error occurred = 1

[4..4] ...

Definition at line 26801 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::f_type3

[18..18] Type II error (transmission layer) triggers F type III. Error recognition occurs in the EnDat master. The error did not occur = 0 The error occurred = 1

[18..18] ...

Definition at line 26850 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::filter

[21..19] The digital filter for the Data_RC data input can be adjusted in eight steps (3 bits) as shown in the table below. The filter setting value corresponds to system clock cycles. Setting 000 = Off Setting 001 = 3 Setting 010 = 4 Setting 011 = 5 Setting 100 = 6 Setting 101 = 10 Setting 110 = 20 Setting 111 = 40 Setting 000 001 010 011 100 101 110 111 Note on the application: The filter must be set according to the transmission rate of the serial interface to the encoder.

Definition at line 26719 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::format

[1..1] Here the transmission format for SSI transmission is selected. Fir tree: 0 Serial, right-aligned = 1

Definition at line 26751 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::gray_to_binary

[2..2] In SSI transmission mode, Gray code values can be converted here to binary code values. Gray-to-binary conversion inactive = 0 Gray-to-binary conversion inactive = 1

Definition at line 26753 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::hw_strobe

[0..0] 1: Enables external /STR signal as strobe signal

Definition at line 26632 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::hw_strobe_delay

[31..24] Here the application can enter a value for the HW strobe delay. The binary value has a step width of one system clock. Setting 00 = Off, 3..255=3..255 system clock cycles The values 1, 2 are not permissible. At a system clock of 64 MHz, this corresponds to a value range from 46.88 ns to 3.98 us in steps of 15.6 ns.

Definition at line 26736 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ic_reset

[29..29] Setting of this bit has the effect that the entire interface component is reset to its initial state. IC reset inactive = 0 IC reset active = 1

Definition at line 26695 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ic_test_data

[31..16] RTM value - Counter value of the recovery time measurement if conf2(22)=1. Updated after the completion of the recovery time tm measurement during the EnDat transmission with mode command 1-1 'Encoder transmit position value and selection of memory area' with MRS code 0x43 (selection of 2nd word of position value 2). With conf2(22)=0, data for the recovery time measurement tm are not valid. Writing to the test register sets the internal counter of the recovery time measurement to the value of the 'write da

Definition at line 27002 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ic_test_mode

[7..7] The IC can be switched to a special test mode, allowing the testing of internal modules Standard application mode = 0 Special test mode = 1

Definition at line 26973 of file netx90_app.h.

__IM uint32_t endat1_app_Type::ic_test_values

[31..10] ...

Definition at line 26950 of file netx90_app.h.

__IM uint32_t endat1_app_Type::id

[31..0] ...

Definition at line 27060 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ir6

[6..6] This bit indicates an H/L edge at input pin /IR6. No H/L edge transition at input /IR6 = 0 H/L edge transition has occurred at input /IR6R6 = 1

[6..6] ...

Definition at line 26813 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ir7

[7..7] This bit indicates the state of input pin /IR7. Input /IR7 is at high level = 0 Input /IR7 is at low level = 1

[7..7] ...

Definition at line 26816 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::mrs_adr

[5..5] The occurrence of an addressing or acknowledgement error is shown here as described in the EnDat Interface specification. The errors (F type I / II) are special cases of MRS/address errors, i.e. they are a sub-quantity of these. Accordingly, whenever a type I or type II error is identified, the MRS/Adr bit is set. For example, if an MRS/address bit is recognized incorrectly due to a disturbance, only the MRS/Adr status bit will be set, not the F TYP I/II bits. No acknowledgement or addressing error has occ

[5..5] ...

Definition at line 26804 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::parity

[0..0] Here the parity check for SSI transmission is selected. Parity off = 0 Parity on = 1

Definition at line 26749 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::prop_time_measurement

[23..23] (LZM). This bit reports that propagation time measurement was successfully completed. Condition: propagation delay compensation LZK in conf_reg1 is set. If the value for propagation delay compensation in configuration register 1 is corrected by the application, this bit will automatically be reset. LZM incomplete = 0 LZM complete = 1

Definition at line 26862 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ready

[31..31] If the ready bit is set, the status register is completely updated. All checks have been performed. Data transmission is not yet completed, however, meaning that the EnDat protocol automation machine is not yet ready again. No Ready = 0 Ready = 1

[31..31] ...

Definition at line 26890 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::ready_for_strobe

[30..30] This bit reports that data transmission has ended and that the EnDat protocol automation machine is ready for the next transmission. The time values Recovery time 1 (tm) and Recovery time 2 (tR) as specified in the EnDat specification are completed. No Ready = 0 Ready = 1 This bit cannot be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines. The bit cannot cause an interrupt.

Definition at line 26882 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::receive1_reg

[0..0] This status flag indicates that the data in Receive-Reg 1 has been updated. It must be cleared after Receive-Reg1 has been read to allow the interface component to rewrite data there. Receive-Reg1 not updated = 0 Receive-Reg1 updated = 1 Note: This flag is ignored if the uncond_transfer bit is enabled in conf-Reg 1.

[0..0] ...

Definition at line 26784 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::receive2_reg

[8..8] This status flag indicates that the data in Receive-Reg 2 (3) has been updated. It must be cleared after Receive-Reg2 (3) has been read to allow the interface component to rewrite data. Receive-Reg2 (3) not updated = 0 Receive-Reg2 (3) updated = 1

[8..8] ...

Definition at line 26819 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::receive3_reg

[9..9] This status flag indicates that the data in Receive-Reg3 has been updated. It must be cleared after Receive-Reg3 has been read to allow the interface component to rewrite data. Receive-Reg3 not updated = 0 Receive-Reg3 updated = 1

[9..9] ...

Definition at line 26824 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::reset_window

[14..14] The set bit allows resetting of the status and error register only within a defined time period. Reset window = 0 Resetting of the registers mentioned above can be performed anytime (i.e. without considering malfunctions). Reset Window = 1 Resetting of the registers mentioned above must be performed within a defined time period for acceptance by the protocol engine. For safety applications: reset window = 1

Definition at line 26659 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::rm

[14..14] Contains the RM status bit as transmitted in the EnDat protocol. RM = 0 RM = 1

Definition at line 26840 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::RM

[14..14] ...

Definition at line 26925 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::rtm

[22..22] Activates the recovery time measurement that is then performed after each EnDat transmission with the mode command 1-1 'Encoder transmit position value and selection of memory area' with MRS code 0x43 (selection of 2nd word of position value 2). RTM=0 Recovery time measurement is deactivated (default setting after reset) RTM=1 Recovery time measurement is activated

Definition at line 26728 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::rtm_start

[27..27] This bit indicates the beginning of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 'Encoder transmit position value and selection of memory area' with MRS code 0x43 (selection of 2nd word of position value 2)

Definition at line 26869 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::rtm_stop

[28..28] This bit indicates the end of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 'Encoder transmit position value and selection of memory area' with MRS code 0x43 (selection of 2nd word of position value 2)

Definition at line 26874 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::sel_test_mux

[5..4] (for testing at IC manufacturing site, internal resources can be read) Standard operating mode = 00 Central pre-dividers = 01 Start bit counter = 10 Delay counter and register, additional information bit = 11

Definition at line 26968 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::sel_test_mux2

[13..12] (For testing at IC manufacturing site, internal resources can be read via test register 4) Test_Mode_Divider = 0: Selection of test multiplexer 2: Test value Pos1b (Pos1

Off2) = 00 Test value Pos1c (Pos1 DIV nsrPos1) = 01 Test value Pos1d (Pos1 MOD srM) = 10 Test value Pos2 = 11 Test_Mode_Divider = 1 Selection of test multiplexer 2: Test value quotient (divider) = 00 Test value remainder (divider) = 01

Definition at line 26987 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::sel_test_mux3

[15..14] (For testing at IC manufacturing site, internal resources can be read via test register 3) Write value test register 3 = 00 (Content written to test register 3 via the I/O port.) Test values counter TM measurement = 01 TM_High_Err & TM_low_Err & F_TM & TM_CT2 &TM_CT1 Limit values for TM measurement = 10 C_WT_HIGH & C_WT_LOW & C_HIGH & C_LOW Test values internal OEM Reg = 11 (only available in customer-specific versions)

Definition at line 26994 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::selection_add_info

[10..8] The number of required additional information units (ZI) can also be selected manually(alternatively to implemented ZI automation resources) Automated resources active = 0 00 IC sends clocks for one unit of additional information 1 = 0 01 IC sends clocks for one unit of additional information 2 = 0 10 IC sends clocks for two units of additional information (1+2) = 0 11 IC sends no clocks for additional information = 1 xx

Definition at line 26976 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::selection_tst_out

[2..2] For testing, the TST_OUT_PIN pin is assigned as follows: Internal (delayed by synchronization) DATA_RC_INT = 0 This signal is the signal that belongs to data strobe pulse.

Definition at line 26959 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::singleturn_res

[7..3] Here the number of steps per revolution is set to binary with 5 bits. This setting is only required for the fir tree format. Singleturn resolution = 13 bits = 0 1101

Definition at line 26756 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::speed

[15..15] (optional) This bit allows selection of the register width for velocity. 64-bit = 0 32-Bit = 1

Definition at line 26763 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::speed_ready

[29..29] (optional). This bit reports that a new velocity value has been calculated. No new velocity value calculated = 0 New velocity value calculated = 1

[29..29] ...

Definition at line 26879 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::spike

[16..16] Reports that a Spike was detected at the data input port. Condition: filter in conf_reg1 is set. No spike = 0 Spike occurred = 1

[16..16] ...

Definition at line 26844 of file netx90_app.h.

__IM uint32_t endat1_app_Type::status_zi

[2..1] Allows testing of the IC-internal automation machine. IC sends no clocks for additional information = 00 IC sends clocks for one unit of additional information 1 = 01 IC sends clocks for one unit of additional information 2 = 10 IC sends clocks for two units of additional information (1+2) = 11

Definition at line 26942 of file netx90_app.h.

__OM uint32_t endat1_app_Type::sw_strobe

[31..0] Writing this register will in each case cause the first H/L transition of the TCLK transmission clock signal.

Definition at line 27044 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::t_st

[18..16] This time is to be set in accordance with EnDat specification. The set time has an accuracy of 0.1 us. Setting 000 = 0.5 TCLK Setting 001 = 0.5 us Setting 010 = 1 us Setting 011 = 1.5 us Setting 100 = 2 us Setting 101 = 4 us Setting 110 = 8 us Setting 111 = 10 us

Definition at line 26714 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::test_mode_divider

[11..11] (For testing at IC manufacturing site, internal resources can be read via test register 4) Standard operating mode = 0 Test mode active = 1

Definition at line 26984 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::test_receive_reg

[3..3] Standard operating mode = TST receive_reg = 0 Test mode for receive register = TST receive_reg = 1 By writing to the address of the receive registers, the content of test register 2 (bits (31:16) is transferred them. It is not possible to directly write to a receive register via the parallel port.

Definition at line 26962 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::timer_for_sampling_rate

[7..0] 256 different sampling rates can be set. In the default setting 00 hex or 80 hex the timer is off.

Definition at line 26710 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::uncond_transfer

[1..1] This bit defines the unconditional data transfer to receive registers 1, 2, 3, 4 on completion of a data transmission process, despite a flag being set in the status register. Data transfer according to flag set in the status register = 0 Data transfer despite the flag in the status register = 1 For safety applications uncond_transfer = 1 must be set.

Definition at line 26633 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::watchdog

[15..8] 256 different watchdog time values can be set. In the default setting 00 hex or 80 hex the watchdog is off.

[17..17] Reports triggering of the watchdog. Condition: watchdog in conf_reg2 is set. Watchdog not triggered = 0 Watchdog triggered = 1

[17..17] ...

Definition at line 26712 of file netx90_app.h.

__IOM uint32_t endat1_app_Type::wrn

[15..15] Contains the WRN status bit as transmitted in the EnDat protocol. WRN = 0 WRN = 1

[15..15] ...

Definition at line 26842 of file netx90_app.h.

The documentation for this struct was generated from the following file:

netx90_app.h

Data Fields

Detailed Description

Field Documentation