ecc_ctrl_Type Struct Reference

ecc_ctrl (ecc_ctrl) More...

#include <netx90_app.h>

Collaboration diagram for ecc_ctrl_Type:

Data Fields
union {
__IOM uint32_t   ecc_ctrl_iflash2_ctrl
struct {
__IOM uint32_t   enable: 1
__IOM uint32_t   syndrome_inv: 8
__IOM uint32_t   bf_align0: 23
}   ecc_ctrl_iflash2_ctrl_b
};
union {
__IM uint32_t   ecc_ctrl_iflash2_addr_sbe
struct {
__IM uint32_t   address: 15
__IM uint32_t   bf_align0: 17
}   ecc_ctrl_iflash2_addr_sbe_b
};
union {
__IM uint32_t   ecc_ctrl_iflash2_addr_dbe
struct {
__IM uint32_t   address: 15
__IM uint32_t   bf_align0: 17
}   ecc_ctrl_iflash2_addr_dbe_b
};
union {
__IOM uint32_t   ecc_ctrl_status_sbe
struct {
__IOM uint32_t   iflash2: 1
__IOM uint32_t   bf_align0: 31
}   ecc_ctrl_status_sbe_b
};
union {
__IOM uint32_t   ecc_ctrl_status_dbe
struct {
__IOM uint32_t   iflash2: 1
__IOM uint32_t   bf_align0: 31
}   ecc_ctrl_status_dbe_b
};

Detailed Description

ecc_ctrl (ecc_ctrl)

Definition at line 17169 of file netx90_app.h.

Field Documentation

union { ... }

< (@ 0xFF401780) ecc_ctrl Structure

union { ... }

union { ... }

union { ... }

union { ... }

__IM uint32_t ecc_ctrl_Type::address

[14..0] Address of last ECC single bit error

[14..0] Address of last ECC double bit error

Definition at line 17195 of file netx90_app.h.

__IOM uint32_t ecc_ctrl_Type::bf_align0

[31..9] bitField alignment value for aeabi compatibility

[31..1] bitField alignment value for aeabi compatibility

Definition at line 17177 of file netx90_app.h.

__IM uint32_t ecc_ctrl_Type::bf_align0

[31..15] bitField alignment value for aeabi compatibility

Definition at line 17196 of file netx90_app.h.

__IM uint32_t ecc_ctrl_Type::ecc_ctrl_iflash2_addr_dbe

(@ 0x00000008) RAM Address of ECC single bit error (DBE): This register logs the RAM address where first ECC DBE occured. This first DBE address will be stored (even in case of further DBEs) until the appropriate bit in status_sbe register was cleared. Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs or RAMs that are not directly accessible by CPU.

Definition at line 17201 of file netx90_app.h.

struct { ... } ecc_ctrl_Type::ecc_ctrl_iflash2_addr_dbe_b

__IM uint32_t ecc_ctrl_Type::ecc_ctrl_iflash2_addr_sbe

(@ 0x00000004) RAM Address of ECC single bit error (SBE): This register logs the RAM address where first ECC SBE occured. This first SBE address will be stored (even in case of further SBEs) until the appropriate bit in status_sbe register was cleared. Note1: Not all RAM ECCs support error address logging, e.g. dual-port RAMs Note2: This is the real RAM address, i.e. a 32-bit address except at xMAC 64-bit RAMs or RAMs that are not directly accessible by CPU.

Definition at line 17182 of file netx90_app.h.

struct { ... } ecc_ctrl_Type::ecc_ctrl_iflash2_addr_sbe_b

__IOM uint32_t ecc_ctrl_Type::ecc_ctrl_iflash2_ctrl

(@ 0x00000000) IFLASH2 syndrome manipulation register

Definition at line 17172 of file netx90_app.h.

struct { ... } ecc_ctrl_Type::ecc_ctrl_iflash2_ctrl_b

__IOM uint32_t ecc_ctrl_Type::ecc_ctrl_status_dbe

(@ 0x00000010) ECC status DBE: This register collects double bit error (DBE) status information. In case of ECC DBE, a bit of the appropriate RAM in this register will be set. Bits can be reset by writing '1' to the apprpriate bit position (write to clear). If a SBE or DBE bit is set, IRQ signal will be asserted. Note: No mask register is required, as error correction can be enabled for each RAM separately.

Definition at line 17237 of file netx90_app.h.

struct { ... } ecc_ctrl_Type::ecc_ctrl_status_dbe_b

__IOM uint32_t ecc_ctrl_Type::ecc_ctrl_status_sbe

(@ 0x0000000C) ECC status SBE: This register collects single bit error (SBE) status information. In case of ECC SBE, a bit in this register will be set. Bits can be reset by writing '1' to the apprpriate bit position (write to clear). If a SBE or DBE bit is set, IRQ signal will be asserted. Note: No mask register is required, as error correction can be enabled for each RAM separately.

Definition at line 17220 of file netx90_app.h.

struct { ... } ecc_ctrl_Type::ecc_ctrl_status_sbe_b

__IOM uint32_t ecc_ctrl_Type::enable

[0..0] enable ECC

Definition at line 17175 of file netx90_app.h.

__IOM uint32_t ecc_ctrl_Type::iflash2

[0..0] IFLASH2 Single Bit Error occured

[0..0] IFLASH2 Double Bit Error occured

Definition at line 17231 of file netx90_app.h.

__IOM uint32_t ecc_ctrl_Type::syndrome_inv

[8..1] Inverts syndrome bits for ECC testing

Definition at line 17176 of file netx90_app.h.

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The documentation for this struct was generated from the following file:

• netx90_app.h