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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
cm4_misc_ctrl (cm4_misc_ctrl) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IM uint32_t cm4_misc_ctrl_cpu_info | |
| struct { | |
| __IM uint32_t id: 1 | |
| __IM uint32_t fpu: 1 | |
| __IM uint32_t bf_align0: 30 | |
| } cm4_misc_ctrl_cpu_info_b | |
| }; | |
| union { | |
| __IOM uint32_t cm4_misc_ctrl_fpu_irq_raw | |
| struct { | |
| __IOM uint32_t ixc: 1 | |
| __IOM uint32_t ufc: 1 | |
| __IOM uint32_t ofc: 1 | |
| __IOM uint32_t dzc: 1 | |
| __IOM uint32_t ioc: 1 | |
| __IOM uint32_t idc: 1 | |
| __IOM uint32_t bf_align0: 26 | |
| } cm4_misc_ctrl_fpu_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t cm4_misc_ctrl_fpu_irq_masked | |
| struct { | |
| __IM uint32_t ixc: 1 | |
| __IM uint32_t ufc: 1 | |
| __IM uint32_t ofc: 1 | |
| __IM uint32_t dzc: 1 | |
| __IM uint32_t ioc: 1 | |
| __IM uint32_t idc: 1 | |
| __IM uint32_t bf_align0: 26 | |
| } cm4_misc_ctrl_fpu_irq_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t cm4_misc_ctrl_fpu_irq_msk_set | |
| struct { | |
| __IOM uint32_t ixc: 1 | |
| __IOM uint32_t ufc: 1 | |
| __IOM uint32_t ofc: 1 | |
| __IOM uint32_t dzc: 1 | |
| __IOM uint32_t ioc: 1 | |
| __IOM uint32_t idc: 1 | |
| __IOM uint32_t bf_align0: 26 | |
| } cm4_misc_ctrl_fpu_irq_msk_set_b | |
| }; | |
| union { | |
| __IOM uint32_t cm4_misc_ctrl_fpu_irq_msk_reset | |
| struct { | |
| __IOM uint32_t ixc: 1 | |
| __IOM uint32_t ufc: 1 | |
| __IOM uint32_t ofc: 1 | |
| __IOM uint32_t dzc: 1 | |
| __IOM uint32_t ioc: 1 | |
| __IOM uint32_t idc: 1 | |
| __IOM uint32_t bf_align0: 26 | |
| } cm4_misc_ctrl_fpu_irq_msk_reset_b | |
| }; | |
cm4_misc_ctrl (cm4_misc_ctrl)
Definition at line 1302 of file netx90_app.h.
| union { ... } |
< (@ 0xE0043000) cm4_misc_ctrl Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IM uint32_t cm4_misc_ctrl_Type::bf_align0 |
[31..2] bitField alignment value for aeabi compatibility
[31..6] bitField alignment value for aeabi compatibility
Definition at line 1313 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::bf_align0 |
[31..6] bitField alignment value for aeabi compatibility
Definition at line 1335 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::cm4_misc_ctrl_cpu_info |
(@ 0x00000000) CPU information register Provides a processor identification mechanism to distinguish between Com ARM and App ARM.
Definition at line 1305 of file netx90_app.h.
| struct { ... } cm4_misc_ctrl_Type::cm4_misc_ctrl_cpu_info_b |
| __IM uint32_t cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_masked |
(@ 0x00000008) FPU masked IRQ Shows status of masked IRQs.
Definition at line 1340 of file netx90_app.h.
| struct { ... } cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_masked_b |
| __IOM uint32_t cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_msk_reset |
(@ 0x00000010) FPU IRQ mask reset This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 1378 of file netx90_app.h.
| struct { ... } cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_msk_reset_b |
| __IOM uint32_t cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_msk_set |
(@ 0x0000000C) FPU IRQ mask set The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to cm4_misc_ctrl_fpu_irq
Definition at line 1354 of file netx90_app.h.
| struct { ... } cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_msk_set_b |
| __IOM uint32_t cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_raw |
(@ 0x00000004) FPU raw IRQ Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ. Write access with '0' does not influence this bit. Note: Before clearing an IRQ in this register, the corresponding exception status must be cleared within the FPU. Otherwise the IRQ will be re-asserted immediately.
Definition at line 1318 of file netx90_app.h.
| struct { ... } cm4_misc_ctrl_Type::cm4_misc_ctrl_fpu_irq_raw_b |
| __IOM uint32_t cm4_misc_ctrl_Type::dzc |
[3..3] Division by zero (IEEE 754-2008 defined exception).
Definition at line 1332 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::dzc |
[3..3] Division by zero (IEEE 754-2008 defined exception).
Definition at line 1346 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::fpu |
[1..1] CPU has FPU If '0' all cm4_misc_ctrl_fpu_* registers have no effect and are read as zero.
Definition at line 1311 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::id |
[0..0] CPU identification 0: Com ARM 1: App ARM
Definition at line 1310 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::idc |
[5..5] Input denormal (ARM-specific exception).
Definition at line 1334 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::idc |
[5..5] Input denormal (ARM-specific exception).
Definition at line 1348 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::ioc |
[4..4] Invalid operation (IEEE 754-2008 defined exception).
Definition at line 1333 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::ioc |
[4..4] Invalid operation (IEEE 754-2008 defined exception).
Definition at line 1347 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::ixc |
[0..0] Inexact (IEEE 754-2008 defined exception).
Definition at line 1329 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::ixc |
[0..0] Inexact (IEEE 754-2008 defined exception).
Definition at line 1343 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::ofc |
[2..2] Overflow (IEEE 754-2008 defined exception).
Definition at line 1331 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::ofc |
[2..2] Overflow (IEEE 754-2008 defined exception).
Definition at line 1345 of file netx90_app.h.
| __IOM uint32_t cm4_misc_ctrl_Type::ufc |
[1..1] Underflow (IEEE 754-2008 defined exception).
Definition at line 1330 of file netx90_app.h.
| __IM uint32_t cm4_misc_ctrl_Type::ufc |
[1..1] Underflow (IEEE 754-2008 defined exception).
Definition at line 1344 of file netx90_app.h.
1.8.11