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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
biss_ctrl1_app (biss_ctrl1_app) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IOM uint32_t biss_ctrl_trigger_cfg | |
| struct { | |
| __IOM uint32_t sel: 4 | |
| __IOM uint32_t bf_align0: 28 | |
| } biss_ctrl_trigger_cfg_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ctrl_trigger | |
| struct { | |
| __IOM uint32_t manual: 1 | |
| __IOM uint32_t bf_align0: 31 | |
| } biss_ctrl_trigger_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ctrl_irq_raw | |
| struct { | |
| __IOM uint32_t eot: 1 | |
| __IOM uint32_t err: 1 | |
| __IOM uint32_t bf_align0: 30 | |
| } biss_ctrl_irq_raw_b | |
| }; | |
| union { | |
| __IM uint32_t biss_ctrl_irq_masked | |
| struct { | |
| __IM uint32_t eot: 1 | |
| __IM uint32_t err: 1 | |
| __IM uint32_t bf_align0: 30 | |
| } biss_ctrl_irq_masked_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ctrl_irq_msk_set | |
| struct { | |
| __IOM uint32_t eot: 1 | |
| __IOM uint32_t err: 1 | |
| __IOM uint32_t bf_align0: 30 | |
| } biss_ctrl_irq_msk_set_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ctrl_irq_msk_reset | |
| struct { | |
| __IOM uint32_t eot: 1 | |
| __IOM uint32_t err: 1 | |
| __IOM uint32_t bf_align0: 30 | |
| } biss_ctrl_irq_msk_reset_b | |
| }; | |
biss_ctrl1_app (biss_ctrl1_app)
Definition at line 27311 of file netx90_app.h.
| union { ... } |
< (@ 0xFF8020C0) biss_ctrl1_app Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IOM uint32_t biss_ctrl1_app_Type::bf_align0 |
[31..4] bitField alignment value for aeabi compatibility
[31..1] bitField alignment value for aeabi compatibility
[31..2] bitField alignment value for aeabi compatibility
Definition at line 27325 of file netx90_app.h.
| __IM uint32_t biss_ctrl1_app_Type::bf_align0 |
[31..2] bitField alignment value for aeabi compatibility
Definition at line 27364 of file netx90_app.h.
| __IM uint32_t biss_ctrl1_app_Type::biss_ctrl_irq_masked |
(@ 0x0000000C) BiSS masked IRQ: Shows status of masked IRQs.
Definition at line 27359 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_irq_masked_b |
| __IOM uint32_t biss_ctrl1_app_Type::biss_ctrl_irq_msk_reset |
(@ 0x00000014) BiSS IRQ mask reset: This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources: Write access with '1' resets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask.
Definition at line 27389 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_irq_msk_reset_b |
| __IOM uint32_t biss_ctrl1_app_Type::biss_ctrl_irq_msk_set |
(@ 0x00000010) BiSS IRQ mask set: The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks: Write access with '1' sets interrupt mask bit. Write access with '0' does not influence this bit. Read access shows actual interrupt mask. Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
Definition at line 27369 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_irq_msk_set_b |
| __IOM uint32_t biss_ctrl1_app_Type::biss_ctrl_irq_raw |
(@ 0x00000008) BiSS raw IRQ: Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register: Write access with '1' resets the appropriate IRQ. Write access with '0' does not influence this bit.
Definition at line 27342 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_irq_raw_b |
| __IOM uint32_t biss_ctrl1_app_Type::biss_ctrl_trigger |
(@ 0x00000004) BiSS trigger
Definition at line 27330 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_trigger_b |
| __IOM uint32_t biss_ctrl1_app_Type::biss_ctrl_trigger_cfg |
(@ 0x00000000) BiSS trigger configuration
Definition at line 27314 of file netx90_app.h.
| struct { ... } biss_ctrl1_app_Type::biss_ctrl_trigger_cfg_b |
| __IOM uint32_t biss_ctrl1_app_Type::eot |
[0..0] End-Of-Transmission signal from the BiSS core. Only a rising edge on the EOT signal will set the interrupt.
[0..0] End-Of-Transmission signal from the BiSS core.
Definition at line 27350 of file netx90_app.h.
| __IM uint32_t biss_ctrl1_app_Type::eot |
[0..0] End-Of-Transmission signal from the BiSS core.
Definition at line 27362 of file netx90_app.h.
| __IOM uint32_t biss_ctrl1_app_Type::err |
[1..1] Error signal from the BiSS core. Only a falling edge on the NER signal will set the interrupt.
[1..1] Error signal from the BiSS core.
Definition at line 27352 of file netx90_app.h.
| __IM uint32_t biss_ctrl1_app_Type::err |
[1..1] Error signal from the BiSS core.
Definition at line 27363 of file netx90_app.h.
| __IOM uint32_t biss_ctrl1_app_Type::manual |
[0..0] Manual trigger. Writing '1' to this bit will trigger the BiSS core immediately in case the trigger_cfg.sel bit field is set to manual mode and the BiSS core is setup for external triggering by the GETSENS signal.
Definition at line 27333 of file netx90_app.h.
| __IOM uint32_t biss_ctrl1_app_Type::sel |
[3..0] Trigger source select This bit field configures which event is connected to the GETSENS signal of the BiSS core. A rising edge of the selected event will generate an event to the core. { | Value trigger event 0 none 1 manual 2 xc_trigger_out0 3 xc_trigger_out0 (inverted) 4 xc_trigger_out1 5 xc_trigger_out1 (inverted) 6 xc_sample_in0 7 xc_sample_in0 (inverted) 8 xc_sample_in1 9 xc_sample_in1 (inverted) 10 gpio_app_counter_zero0 11
Definition at line 27317 of file netx90_app.h.
1.8.11