 |
Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
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Hilscher netX microcontroller driver
V0.0.5.0
Documentation of the netX driver package
|
biss1_app (biss1_app) More...
#include <netx90_app.h>
Data Fields | |
| union { | |
| __IOM uint32_t biss_scdata0_0 | |
| struct { | |
| __IOM uint32_t SCDATA0_0: 32 | |
| } biss_scdata0_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata0_1 | |
| struct { | |
| __IOM uint32_t SCDATA0_1: 32 | |
| } biss_scdata0_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata1_0 | |
| struct { | |
| __IOM uint32_t SCDATA1_0: 32 | |
| } biss_scdata1_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata1_1 | |
| struct { | |
| __IOM uint32_t SCDATA1_1: 32 | |
| } biss_scdata1_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata2_0 | |
| struct { | |
| __IOM uint32_t SCDATA2_0: 32 | |
| } biss_scdata2_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata2_1 | |
| struct { | |
| __IOM uint32_t SCDATA2_1: 32 | |
| } biss_scdata2_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata3_0 | |
| struct { | |
| __IOM uint32_t SCDATA3_0: 32 | |
| } biss_scdata3_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata3_1 | |
| struct { | |
| __IOM uint32_t SCDATA3_1: 32 | |
| } biss_scdata3_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata4_0 | |
| struct { | |
| __IOM uint32_t SCDATA4_0: 32 | |
| } biss_scdata4_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata4_1 | |
| struct { | |
| __IOM uint32_t SCDATA4_1: 32 | |
| } biss_scdata4_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata5_0 | |
| struct { | |
| __IOM uint32_t SCDATA5_0: 32 | |
| } biss_scdata5_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata5_1 | |
| struct { | |
| __IOM uint32_t SCDATA5_1: 32 | |
| } biss_scdata5_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata6_0 | |
| struct { | |
| __IOM uint32_t SCDATA6_0: 32 | |
| } biss_scdata6_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata6_1 | |
| struct { | |
| __IOM uint32_t SCDATA6_1: 32 | |
| } biss_scdata6_1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata7_0 | |
| struct { | |
| __IOM uint32_t SCDATA7_0: 32 | |
| } biss_scdata7_0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_scdata7_1 | |
| struct { | |
| __IOM uint32_t SCDATA7_1: 32 | |
| } biss_scdata7_1_b | |
| }; | |
| __IM uint32_t | RESERVED [16] |
| union { | |
| __IOM uint32_t biss_rdata0 | |
| struct { | |
| __IOM uint32_t RDATA0: 32 | |
| } biss_rdata0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata1 | |
| struct { | |
| __IOM uint32_t RDATA1: 32 | |
| } biss_rdata1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata2 | |
| struct { | |
| __IOM uint32_t RDATA2: 32 | |
| } biss_rdata2_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata3 | |
| struct { | |
| __IOM uint32_t RDATA3: 32 | |
| } biss_rdata3_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata4 | |
| struct { | |
| __IOM uint32_t RDATA4: 32 | |
| } biss_rdata4_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata5 | |
| struct { | |
| __IOM uint32_t RDATA5: 32 | |
| } biss_rdata5_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata6 | |
| struct { | |
| __IOM uint32_t RDATA6: 32 | |
| } biss_rdata6_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata7 | |
| struct { | |
| __IOM uint32_t RDATA7: 32 | |
| } biss_rdata7_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata8 | |
| struct { | |
| __IOM uint32_t RDATA8: 32 | |
| } biss_rdata8_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata9 | |
| struct { | |
| __IOM uint32_t RDATA9: 32 | |
| } biss_rdata9_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata10 | |
| struct { | |
| __IOM uint32_t RDATA10: 32 | |
| } biss_rdata10_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata11 | |
| struct { | |
| __IOM uint32_t RDATA11: 32 | |
| } biss_rdata11_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata12 | |
| struct { | |
| __IOM uint32_t RDATA12: 32 | |
| } biss_rdata12_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata13 | |
| struct { | |
| __IOM uint32_t RDATA13: 32 | |
| } biss_rdata13_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata14 | |
| struct { | |
| __IOM uint32_t RDATA14: 32 | |
| } biss_rdata14_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_rdata15 | |
| struct { | |
| __IOM uint32_t RDATA15: 32 | |
| } biss_rdata15_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc0 | |
| struct { | |
| __IOM uint32_t SCDLEN0: 6 | |
| __IOM uint32_t ENSCD0: 1 | |
| __IOM uint32_t LSTOP0: 1 | |
| __IOM uint32_t SCRCPOLY0: 7 | |
| __IOM uint32_t SELCRCS0: 1 | |
| __IOM uint32_t SCRCSTART0: 16 | |
| } biss_sc0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc1 | |
| struct { | |
| __IOM uint32_t SCDLEN1: 6 | |
| __IOM uint32_t ENSCD1: 1 | |
| __IOM uint32_t LSTOP1: 1 | |
| __IOM uint32_t SCRCPOLY1: 7 | |
| __IOM uint32_t SELCRCS1: 1 | |
| __IOM uint32_t SCRCSTART1: 16 | |
| } biss_sc1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc2 | |
| struct { | |
| __IOM uint32_t SCDLEN2: 6 | |
| __IOM uint32_t ENSCD2: 1 | |
| __IOM uint32_t LSTOP2: 1 | |
| __IOM uint32_t SCRCPOLY2: 7 | |
| __IOM uint32_t SELCRCS2: 1 | |
| __IOM uint32_t SCRCSTART2: 16 | |
| } biss_sc2_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc3 | |
| struct { | |
| __IOM uint32_t SCDLEN3: 6 | |
| __IOM uint32_t ENSCD3: 1 | |
| __IOM uint32_t LSTOP3: 1 | |
| __IOM uint32_t SCRCPOLY3: 7 | |
| __IOM uint32_t SELCRCS3: 1 | |
| __IOM uint32_t SCRCSTART3: 16 | |
| } biss_sc3_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc4 | |
| struct { | |
| __IOM uint32_t SCDLEN4: 6 | |
| __IOM uint32_t ENSCD4: 1 | |
| __IOM uint32_t LSTOP4: 1 | |
| __IOM uint32_t SCRCPOLY4: 7 | |
| __IOM uint32_t SELCRCS4: 1 | |
| __IOM uint32_t SCRCSTART4: 16 | |
| } biss_sc4_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc5 | |
| struct { | |
| __IOM uint32_t SCDLEN5: 6 | |
| __IOM uint32_t ENSCD5: 1 | |
| __IOM uint32_t LSTOP5: 1 | |
| __IOM uint32_t SCRCPOLY5: 7 | |
| __IOM uint32_t SELCRCS5: 1 | |
| __IOM uint32_t SCRCSTART5: 16 | |
| } biss_sc5_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc6 | |
| struct { | |
| __IOM uint32_t SCDLEN6: 6 | |
| __IOM uint32_t ENSCD6: 1 | |
| __IOM uint32_t LSTOP6: 1 | |
| __IOM uint32_t SCRCPOLY6: 7 | |
| __IOM uint32_t SELCRCS6: 1 | |
| __IOM uint32_t SCRCSTART6: 16 | |
| } biss_sc6_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_sc7 | |
| struct { | |
| __IOM uint32_t SCDLEN7: 6 | |
| __IOM uint32_t ENSC7: 1 | |
| __IOM uint32_t LSTOP7: 1 | |
| __IOM uint32_t SCRCPOLY7: 7 | |
| __IOM uint32_t SELCRCS7: 1 | |
| __IOM uint32_t SCRCSTART7: 16 | |
| } biss_sc7_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ccc0 | |
| struct { | |
| __IOM uint32_t bf_align0: 16 | |
| __IOM uint32_t REGADR: 7 | |
| __IOM uint32_t WNR: 1 | |
| __IOM uint32_t REGNUM: 6 | |
| __IOM uint32_t bf_align1: 2 | |
| } biss_ccc0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ccc1_mc0 | |
| struct { | |
| __IOM uint32_t CHSEL: 2 | |
| __IOM uint32_t bf_align0: 6 | |
| __IOM uint32_t HOLDCDM: 1 | |
| __IOM uint32_t EN_MO: 1 | |
| __IOM uint32_t bf_align1: 1 | |
| __IOM uint32_t IDA_TEST: 1 | |
| __IOM uint32_t CMD: 2 | |
| __IOM uint32_t REGVERS: 1 | |
| __IOM uint32_t CTS: 1 | |
| __IOM uint32_t FREQS: 5 | |
| __IOM uint32_t FREQR: 3 | |
| __IOM uint32_t SINGLEBANK: 1 | |
| __IOM uint32_t NOCRC: 1 | |
| __IOM uint32_t bf_align2: 6 | |
| } biss_ccc1_mc0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_mc1 | |
| struct { | |
| __IOM uint32_t FREQAGS: 8 | |
| __IOM uint32_t MO_BUSY: 8 | |
| __IOM uint32_t REVISION: 8 | |
| __IOM uint32_t VERSION: 8 | |
| } biss_mc1_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_cc_sl | |
| struct { | |
| __IOM uint32_t cc_sl_reserved1: 4 | |
| __IOM uint32_t SLAVELOC5: 1 | |
| __IOM uint32_t bf_align0: 3 | |
| __IOM uint32_t CFGCH1: 2 | |
| __IOM uint32_t CFGCH2: 2 | |
| __IOM uint32_t bf_align1: 12 | |
| __IOM uint32_t ACTnSENS: 8 | |
| } biss_cc_sl_b | |
| }; | |
| union { | |
| __IM uint32_t biss_status0 | |
| struct { | |
| __IM uint32_t EOT: 1 | |
| __IM uint32_t status0_reserved1: 1 | |
| __IM uint32_t REGEND: 1 | |
| __IM uint32_t nREGERR: 1 | |
| __IM uint32_t nSCDERR: 1 | |
| __IM uint32_t nDELAYERR: 1 | |
| __IM uint32_t nAGSERR: 1 | |
| __IM uint32_t nERR: 1 | |
| __IM uint32_t bf_align0: 1 | |
| __IM uint32_t SVALID0: 1 | |
| __IM uint32_t bf_align1: 1 | |
| __IM uint32_t SVALID1: 1 | |
| __IM uint32_t bf_align2: 1 | |
| __IM uint32_t SVALID2: 1 | |
| __IM uint32_t bf_align3: 1 | |
| __IM uint32_t SVALID3: 1 | |
| __IM uint32_t bf_align4: 1 | |
| __IM uint32_t SVALID4: 1 | |
| __IM uint32_t bf_align5: 1 | |
| __IM uint32_t SVALID5: 1 | |
| __IM uint32_t bf_align6: 1 | |
| __IM uint32_t SVALID6: 1 | |
| __IM uint32_t bf_align7: 1 | |
| __IM uint32_t SVALID7: 1 | |
| __IM uint32_t REGBYTES: 6 | |
| __IM uint32_t CDSSEL: 1 | |
| __IM uint32_t CDMTIMEOUT: 1 | |
| } biss_status0_b | |
| }; | |
| union { | |
| __IOM uint32_t biss_ir | |
| struct { | |
| __IOM uint32_t AGS: 1 | |
| __IOM uint32_t INSTR: 3 | |
| __IOM uint32_t INIT: 1 | |
| __IOM uint32_t SWBANK: 1 | |
| __IOM uint32_t HOLDBANK: 1 | |
| __IOM uint32_t BREAK: 1 | |
| __IOM uint32_t CLKENI: 1 | |
| __IOM uint32_t ENTEST: 1 | |
| __IOM uint32_t CFGIF: 2 | |
| __IOM uint32_t MAFS: 1 | |
| __IOM uint32_t MAVS: 1 | |
| __IOM uint32_t MAFO: 1 | |
| __IOM uint32_t MAVO: 1 | |
| __IOM uint32_t bf_align0: 16 | |
| } biss_ir_b | |
| }; | |
| union { | |
| __IM uint32_t biss_status1 | |
| struct { | |
| __IM uint32_t SL1: 1 | |
| __IM uint32_t CDS1: 1 | |
| __IM uint32_t bf_align0: 22 | |
| __IM uint32_t SWBANKFAILS: 1 | |
| __IM uint32_t bf_align1: 7 | |
| } biss_status1_b | |
| }; | |
biss1_app (biss1_app)
Definition at line 28223 of file netx90_app.h.
| union { ... } |
< (@ 0xFF802200) biss1_app Structure
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
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| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| union { ... } |
| __IOM uint32_t biss1_app_Type::ACTnSENS |
[31..24] Sensor or actuator data selector 0x00: all slaves are sensors 0x01: slave 0 is actuator 0x02: slave 1 is actuator 0x04: slave 2 is actuator 0x08: slave 3 is actuator 0x10: slave 4 is actuator 0x20: slave 5 is actuator 0x40: slave 6 is actuator 0x80: slave 7 is actuator 0xff: all slaves are actuators
Definition at line 28852 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::AGS |
[0..0] AutoGetSens(Automatic Get Sensordata) 0: no automatic data transmission 1: - start of data transmission after TIMEOUTSENS condition: FREQAGS = AGSMIN - start of data transmission triggered by pin condition: FREQAGS = AGSINFINITE
Definition at line 28942 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::bf_align0 |
[15..0] bitField alignment value for aeabi compatibility
[7..2] bitField alignment value for aeabi compatibility
[7..5] bitField alignment value for aeabi compatibility
[31..16] bitField alignment value for aeabi compatibility
Definition at line 28753 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align0 |
[8..8] bitField alignment value for aeabi compatibility
[23..2] bitField alignment value for aeabi compatibility
Definition at line 28888 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::bf_align1 |
[31..30] bitField alignment value for aeabi compatibility
[10..10] bitField alignment value for aeabi compatibility
[23..12] bitField alignment value for aeabi compatibility
Definition at line 28759 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align1 |
[10..10] bitField alignment value for aeabi compatibility
[31..25] bitField alignment value for aeabi compatibility
Definition at line 28893 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::bf_align2 |
[31..26] bitField alignment value for aeabi compatibility
Definition at line 28813 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align2 |
[12..12] bitField alignment value for aeabi compatibility
Definition at line 28898 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align3 |
[14..14] bitField alignment value for aeabi compatibility
Definition at line 28903 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align4 |
[16..16] bitField alignment value for aeabi compatibility
Definition at line 28908 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align5 |
[18..18] bitField alignment value for aeabi compatibility
Definition at line 28913 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align6 |
[20..20] bitField alignment value for aeabi compatibility
Definition at line 28918 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::bf_align7 |
[22..22] bitField alignment value for aeabi compatibility
Definition at line 28923 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::biss_cc_sl |
(@ 0x000000EC) Channel Configuration
Definition at line 28839 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_cc_sl_b |
| __IOM uint32_t biss1_app_Type::biss_ccc0 |
(@ 0x000000E0) Register Communication Configuration
Definition at line 28750 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_ccc0_b |
| __IOM uint32_t biss1_app_Type::biss_ccc1_mc0 |
(@ 0x000000E4) Register Communication Configuration / Master Configuration
Definition at line 28764 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_ccc1_mc0_b |
| __IOM uint32_t biss1_app_Type::biss_ir |
(@ 0x000000F4) Instruction Register
Definition at line 28939 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_ir_b |
| __IOM uint32_t biss1_app_Type::biss_mc1 |
(@ 0x000000E8) Master Configuration
Definition at line 28818 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_mc1_b |
| __IOM uint32_t biss1_app_Type::biss_rdata0 |
(@ 0x00000080) Register Data
Definition at line 28355 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata0_b |
| __IOM uint32_t biss1_app_Type::biss_rdata1 |
(@ 0x00000084) Register Data
Definition at line 28366 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::biss_rdata10 |
(@ 0x000000A8) Register Data
Definition at line 28438 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata10_b |
| __IOM uint32_t biss1_app_Type::biss_rdata11 |
(@ 0x000000AC) Register Data
Definition at line 28446 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata11_b |
| __IOM uint32_t biss1_app_Type::biss_rdata12 |
(@ 0x000000B0) Register Data
Definition at line 28454 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata12_b |
| __IOM uint32_t biss1_app_Type::biss_rdata13 |
(@ 0x000000B4) Register Data
Definition at line 28462 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata13_b |
| __IOM uint32_t biss1_app_Type::biss_rdata14 |
(@ 0x000000B8) Register Data
Definition at line 28470 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata14_b |
| __IOM uint32_t biss1_app_Type::biss_rdata15 |
(@ 0x000000BC) Register Data
Definition at line 28478 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata15_b |
| struct { ... } biss1_app_Type::biss_rdata1_b |
| __IOM uint32_t biss1_app_Type::biss_rdata2 |
(@ 0x00000088) Register Data
Definition at line 28374 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata2_b |
| __IOM uint32_t biss1_app_Type::biss_rdata3 |
(@ 0x0000008C) Register Data
Definition at line 28382 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata3_b |
| __IOM uint32_t biss1_app_Type::biss_rdata4 |
(@ 0x00000090) Register Data
Definition at line 28390 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata4_b |
| __IOM uint32_t biss1_app_Type::biss_rdata5 |
(@ 0x00000094) Register Data
Definition at line 28398 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata5_b |
| __IOM uint32_t biss1_app_Type::biss_rdata6 |
(@ 0x00000098) Register Data
Definition at line 28406 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata6_b |
| __IOM uint32_t biss1_app_Type::biss_rdata7 |
(@ 0x0000009C) Register Data
Definition at line 28414 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata7_b |
| __IOM uint32_t biss1_app_Type::biss_rdata8 |
(@ 0x000000A0) Register Data
Definition at line 28422 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata8_b |
| __IOM uint32_t biss1_app_Type::biss_rdata9 |
(@ 0x000000A4) Register Data
Definition at line 28430 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_rdata9_b |
| __IOM uint32_t biss1_app_Type::biss_sc0 |
(@ 0x000000C0) Slave Configuration
Definition at line 28486 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc0_b |
| __IOM uint32_t biss1_app_Type::biss_sc1 |
(@ 0x000000C4) Slave Configuration
Definition at line 28519 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc1_b |
| __IOM uint32_t biss1_app_Type::biss_sc2 |
(@ 0x000000C8) Slave Configuration
Definition at line 28552 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc2_b |
| __IOM uint32_t biss1_app_Type::biss_sc3 |
(@ 0x000000CC) Slave Configuration
Definition at line 28585 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc3_b |
| __IOM uint32_t biss1_app_Type::biss_sc4 |
(@ 0x000000D0) Slave Configuration
Definition at line 28618 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc4_b |
| __IOM uint32_t biss1_app_Type::biss_sc5 |
(@ 0x000000D4) Slave Configuration
Definition at line 28651 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc5_b |
| __IOM uint32_t biss1_app_Type::biss_sc6 |
(@ 0x000000D8) Slave Configuration
Definition at line 28684 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc6_b |
| __IOM uint32_t biss1_app_Type::biss_sc7 |
(@ 0x000000DC) Slave Configuration
Definition at line 28717 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_sc7_b |
| __IOM uint32_t biss1_app_Type::biss_scdata0_0 |
(@ 0x00000000) Sensor and Actuator Data
Definition at line 28226 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata0_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata0_1 |
(@ 0x00000004) Sensor and Actuator Data
Definition at line 28234 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata0_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata1_0 |
(@ 0x00000008) Sensor and Actuator Data
Definition at line 28242 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata1_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata1_1 |
(@ 0x0000000C) Sensor and Actuator Data
Definition at line 28250 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata1_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata2_0 |
(@ 0x00000010) Sensor and Actuator Data
Definition at line 28258 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata2_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata2_1 |
(@ 0x00000014) Sensor and Actuator Data
Definition at line 28266 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata2_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata3_0 |
(@ 0x00000018) Sensor and Actuator Data
Definition at line 28274 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata3_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata3_1 |
(@ 0x0000001C) Sensor and Actuator Data
Definition at line 28282 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata3_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata4_0 |
(@ 0x00000020) Sensor and Actuator Data
Definition at line 28290 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata4_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata4_1 |
(@ 0x00000024) Sensor and Actuator Data
Definition at line 28298 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata4_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata5_0 |
(@ 0x00000028) Sensor and Actuator Data
Definition at line 28306 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata5_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata5_1 |
(@ 0x0000002C) Sensor and Actuator Data
Definition at line 28314 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata5_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata6_0 |
(@ 0x00000030) Sensor and Actuator Data
Definition at line 28322 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata6_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata6_1 |
(@ 0x00000034) Sensor and Actuator Data
Definition at line 28330 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata6_1_b |
| __IOM uint32_t biss1_app_Type::biss_scdata7_0 |
(@ 0x00000038) Sensor and Actuator Data
Definition at line 28338 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata7_0_b |
| __IOM uint32_t biss1_app_Type::biss_scdata7_1 |
(@ 0x0000003C) Sensor and Actuator Data
Definition at line 28346 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_scdata7_1_b |
| __IM uint32_t biss1_app_Type::biss_status0 |
(@ 0x000000F0) Status Information
Definition at line 28862 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_status0_b |
| __IM uint32_t biss1_app_Type::biss_status1 |
(@ 0x000000F8) Status Information
Definition at line 29005 of file netx90_app.h.
| struct { ... } biss1_app_Type::biss_status1_b |
| __IOM uint32_t biss1_app_Type::BREAK |
[7..7] Data transmission interrupt 0: no change 1: abort data transmission nSCDERR, nREGERR, nDELAYERR, nAGSERR = 1, REGEND = 0 All current actions can be aborted using the BREAK command so that a defined state can be resumed if one of the sensors proves faulty, for example. BREAK= 1 aborts the active data transmission and all status information will be reset.
Definition at line 28974 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::cc_sl_reserved1 |
[3..0] no field descpription
Definition at line 28842 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::CDMTIMEOUT |
[31..31] CDM(Control Data Master) timeout reached 0: CDMTIMEOUT not reached 1: CDMTIMEOUT reached
Definition at line 28933 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::CDS1 |
[1..1] CDS bit of channel 1 0: CDS = 0 1: CDS = 1
Definition at line 29010 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::CDSSEL |
[30..30] CDS(Control Data Slave) bit from the selected channel
Definition at line 28932 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CFGCH1 |
[9..8] Channel 1 configuration 0x00: BiSS B 0x01: BiSS C 0x02: SSI 0x03: channel is not used
Definition at line 28847 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CFGCH2 |
[11..10] Channel 2 configuration 0x00: BiSS B 0x01: BiSS C 0x02: SSI 0x03: channel is not used
Definition at line 28849 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CFGIF |
[11..10] Configure physical interface 0x00: TTL 0x01: CMOS 0x02: RS422 0x03: LVDS
Definition at line 28986 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CHSEL |
[1..0] Channel selector 0: channel 1 used for control communication, channel 2 not used 1: channel 1 used for control communication, channel 2 not used 2: channel 2 used for control communication, channel 1 not used. Note: Channel 2 is not available with IC-MB4 TSSOP24 3: channel 1,2 used for control communication. Note: Channel 2 is not available with IC-MB4 TSSOP24
Definition at line 28768 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CLKENI |
[8..8] Enable internal clock 0: the master clock is generated by an external clock oscillator 1: the master clock is generated by the basic clock of the internal 20MHz oscillator
Definition at line 28981 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CMD |
[13..12] - Using register access in control communication SLAVEID[2:1]: slave selector bit2_1 - Using command/instructions in control communication Command of access slave # default 0x00 0x00 .. 0x03: command/instruction 0b00 .. 0b11
Definition at line 28787 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::CTS |
[15..15] Register transmission or instruction selector 0: command/instruction communication 1: register communication
Definition at line 28796 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::EN_MO |
[9..9] Enable output at MOx for actuator data or delayed start bit 0: MO forced to low 1: Parameterized processing time by master on MO signal active (length: MO_BUSY)
Definition at line 28778 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSC7 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28724 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD0 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28493 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD1 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28526 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD2 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28559 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD3 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28592 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD4 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28625 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD5 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28658 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENSCD6 |
[6..6] Enable single cycle data 0: single cycle data not available 1: single cycle data available
Definition at line 28691 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::ENTEST |
[9..9] Enable test interface 0: device in normal operation mode 1: device in test mode
Definition at line 28984 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::EOT |
[0..0] Data transmission completed 0: data transmission active 1: data transmission finished
Definition at line 28865 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::FREQAGS |
[7..0] AutoGetSens Frequency division 0x00.. 0x7b: fCLK/(20*(FREQAGS(6:0)+1)) 0x7c : AGSMIN( the master automatically restarts the next cycle after the prior was finished. AGSMIN is the fastest SCD rate with complete SCD cycles. ) 0x7d.. 0x7f: AGSINFINITE( the master does not automatically restart the next cycle after the prior one was finished. AGSINFINITE requires a trigger event to start the next SCD cycle. ) 0x80.. 0xff: fCLK/(625*(FREQAGS(6:0)+1))
Definition at line 28821 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::FREQR |
[23..21] Frequency division register communication BiSS B 0 .. 7: freqSens/(2*(FREQ(7:5)+1)) 0: FreqSens/2 1: FreqSens/4 2: FreqSens/8 3: FreqSens/16 4: FreqSens/32 5: FreqSens/64 6: FreqSens/128 7: FreqSens/256
Definition at line 28803 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::FREQS |
[20..16] Frequency division 0x00: fCLK/2 0x01: fCLK/4 0x02: fCLK/6 0x03: fCLK/8 ... 0x09: fCLK/20 ... 0x0d: fCLK/28 0x0e: fCLK/30 0x0f: fCLK/32 0x10: not permitted 0x11: fCLK/40 0x12: fCLK/60 0x13: fCLK/80 ... 0x1d: fCLK/280 0x1e: fCLK/300 0x1f: fCLK/320
Definition at line 28798 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::HOLDBANK |
[6..6] RAM bank control 0: no bank switching lock permitted 1: bank switching lock permitted During the readout of more than one sensor data register by the controller it is possible that the RAM banks in the master could be swapped over once a sensor data transmission is completed. So that the controller only reads related values bit HOLDBANK should be set at the start of the readout and reset at the end; this suppresses the RAM swap. With the start of a new sensor data cycle previous values are then overwritten
Definition at line 28965 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::HOLDCDM |
[8..8] Hold CDM(control data master) 0: clock line high at end of cycle 1: clock line constant with CDM bit until start of next cycle
Definition at line 28775 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::IDA_TEST |
[11..11] - Using register access in control communication SLAVEID[0]: slave selector bit0 - Using command/instructions in control communication IDA_TEST: command/instruction execution control 0: the slaves feedback (IDA) is tested before execution (EX bit after IDA) 1: immediate execution
Definition at line 28782 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::INIT |
[4..4] Start INIT sequence 0: no changes on the data channel 1: initialize data channel
Definition at line 28961 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::INSTR |
[3..1] SCD control instruction 0b010 : CDM = 0 0b001 : CDM = 1 0b100, 0b110: register communication condition: CDMTIMEOUT = 1 0b111 : register communication(reduced protocol) condition: CDMTIMEOUT = 1 The transmission of sensor data can be triggered via INSTR. With INSTR=0b010 the ccle finishes with a CDM=0. With INSTR= 0b001 the cycle finishes with a CDM=1. A BiSS C register access to a slave can be operated by INSTR=0b100. A reduced protocol for a shorter BiSS C register access to a slave can
Definition at line 28952 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP0 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28495 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP1 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28528 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP2 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28561 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP3 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28594 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP4 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28627 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP5 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28660 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP6 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28693 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::LSTOP7 |
[7..7] - BISS mode(LSTOPx = Actuator stop bit control) 0: no leading STOP bit on single cycle actuator data 1: leading STOP bit on single cycle actuator data - SSI mode(GRAYSx = Enable SCD gray to binary conversion) 0: SSI single cycle data binary coded 1: SSI single cycle data gray coded
Definition at line 28726 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::MAFO |
[14..14] Not selected MA line control selection 0: controlling unselected(CHSEL) MA clock line: using MA signal 1: controlling unselected(CHSEL) MA clock line: using MAVS level
Definition at line 28994 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::MAFS |
[12..12] Selected MA line control selection 0: controlling selected/CHSEL) MA clock line: using MA signal 1: controlling selected(CHSEL) MA clock line: using MAVS level
Definition at line 28988 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::MAVO |
[15..15] Not selected MA line control level 0: low definition of unselected(CHSEL) MA clock lines 1: high definition of unselected(CHSEL) MA clock lines
Definition at line 28997 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::MAVS |
[13..13] Selected MA line control level 0: low definition of selected(CHSEL) MA clock lines 1: high definition of selected(CHSEL) MA clock lines
Definition at line 28991 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::MO_BUSY |
[15..8] Delay of start bit at output MOx 0x00 .. 0xff: count of MA clocks as the parameterized processing time by master on MO signal Premise: EN_MO = 1
Definition at line 28829 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::nAGSERR |
[6..6] AGS error 0: AGS(Automatic Get Sensor data) watchdog error 1: no AGS watchdog error An AGS watchdog error is set during the automatic transmission of sensor data if no new cycle could be initiated; bit AGS in the command register is reset and the automatic request of sensor data aborted.
Definition at line 28878 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::nDELAYERR |
[5..5] Missing start bit during register communication 0: delay error 1: no delay error
Definition at line 28876 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::nERR |
[7..7] Transmission error (error at NER pin) 0: error 1: no error It is possible to connect other components to pin NER which can also generate an error message; this can then be read out via this bit.
Definition at line 28884 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::NOCRC |
[25..25] CRC for SCD not to be stored in RAM 0: CRC of SCD is stored RAM (only applicable with active CRC verification and CRC polynome > 0) 1: CRC of SCD not to be stored in RAM
Definition at line 28809 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::nREGERR |
[3..3] Error in register data transmission 0: error in last register data transmission 1: no error in last register data transmission
Definition at line 28870 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::nSCDERR |
[4..4] Error in single cycle data transmission 0: error in last single cycle data transmission 1: no error in last single cycle data transmission
Definition at line 28873 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA0 |
[31..0] - Using register access in control communication RDATA0: register data DWord0 - Using command/instructions in control communication IDS: ID-Select, command/instruction addressing combinable
Definition at line 28358 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA1 |
[31..0] register data DWord1
Definition at line 28369 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA10 |
[31..0] register data DWord10
Definition at line 28441 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA11 |
[31..0] register data DWord11
Definition at line 28449 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA12 |
[31..0] register data DWord12
Definition at line 28457 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA13 |
[31..0] register data DWord13
Definition at line 28465 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA14 |
[31..0] register data DWord14
Definition at line 28473 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA15 |
[31..0] register data DWord15
Definition at line 28481 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA2 |
[31..0] register data DWord2
Definition at line 28377 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA3 |
[31..0] register data DWord3
Definition at line 28385 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA4 |
[31..0] register data DWord4
Definition at line 28393 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA5 |
[31..0] register data DWord5
Definition at line 28401 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA6 |
[31..0] register data DWord6
Definition at line 28409 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA7 |
[31..0] register data DWord7
Definition at line 28417 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA8 |
[31..0] register data DWord8
Definition at line 28425 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::RDATA9 |
[31..0] register data DWord9
Definition at line 28433 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::REGADR |
[22..16] Register access start address 0x00 .. 0x7f
Definition at line 28754 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::REGBYTES |
[29..24] Number of valid register data transmission in case of error 0x00 : after transfer: no register communication error 0x01 . 0x3f: after transfer: number of successfully transferred registers before register communication error
Definition at line 28928 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::REGEND |
[2..2] Register data transmission completed 0: no valid register data available 1: register data transmission completed
Definition at line 28868 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::REGNUM |
[29..24] Register data count 0x00 : register count = 1 0x01 ..0x3f: register count = REGNUM(5:0)+1
Definition at line 28757 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::REGVERS |
[14..14] BiSS model A/B or C selector - Using register access in control communication 0: register communication BiSS A/B 1: register communication BiSS C - Using command/instructions in control communication 0: not applicable with command/instruction communication 1: command communication BiSS C
Definition at line 28791 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::RESERVED[16] |
Definition at line 28352 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::REVISION |
[23..16] Revision 0x10: Z(first revision) 0x11: Z1 0x12: Y .. 0xff
Definition at line 28832 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA0_0 |
[31..0] Slave0 (SCD)single cycle data[31:0]
Definition at line 28229 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA0_1 |
[31..0] Slave0 (SCD)single cycle data[63:32]
Definition at line 28237 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA1_0 |
[31..0] Slave1 (SCD)single cycle data[31:0]
Definition at line 28245 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA1_1 |
[31..0] Slave1 (SCD)single cycle data[63:32]
Definition at line 28253 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA2_0 |
[31..0] Slave2 (SCD)single cycle data[31:0]
Definition at line 28261 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA2_1 |
[31..0] Slave2 (SCD)single cycle data[63:32]
Definition at line 28269 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA3_0 |
[31..0] Slave3 (SCD)single cycle data[31:0]
Definition at line 28277 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA3_1 |
[31..0] Slave3 (SCD)single cycle data[63:32]
Definition at line 28285 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA4_0 |
[31..0] Slave4 (SCD)single cycle data[31:0]
Definition at line 28293 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA4_1 |
[31..0] Slave4 (SCD)single cycle data[63:32]
Definition at line 28301 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA5_0 |
[31..0] Slave5 (SCD)single cycle data[31:0]
Definition at line 28309 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA5_1 |
[31..0] Slave5 (SCD)single cycle data[63:32]
Definition at line 28317 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA6_0 |
[31..0] Slave6 (SCD)single cycle data[31:0]
Definition at line 28325 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA6_1 |
[31..0] Slave6 (SCD)single cycle data[63:32]
Definition at line 28333 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA7_0 |
[31..0] Slave0 (SCD)single cycle data[31:0]
Definition at line 28341 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDATA7_1 |
[31..0] Slave7 (SCD)single cycle data[63:32]
Definition at line 28349 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN0 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28489 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN1 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28522 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN2 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28555 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN3 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28588 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN4 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28621 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN5 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28654 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN6 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28687 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCDLEN7 |
[5..0] Single cycle data length 0 : single cycle data length = 1 1 : single cycle data length = 2 ... single cycle data length = SCDLENx + 1 62: single cycle data length = 63 63: single cycle data length = 64
Definition at line 28720 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY0 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28500 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY1 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28533 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY2 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28566 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY3 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28599 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY4 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28632 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY5 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28665 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY6 |
[14..8] - SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with
Definition at line 28698 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCPOLY7 |
[14..8] - SELCRCx == 0 (SCRCLENx: polynomial selection by length for SCD CRC check) 0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0 3: CRC polynomial = 0x0b 4: CRC polynomial = 0x13 5: CRC polynomial = 0x25 6: CRC polynomial = 0x43 7: CRC polynomial = 0x89 8: CRC polynomial = 0x12f 16: CRC polynomial = 0x190d9 ..: other CRC length are not permitted with SELCRCSx = 0 - SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check) 0x00 : CRC polynomial 0x00 not applicable with S
Definition at line 28731 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART0 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28514 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART1 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28547 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART2 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28580 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART3 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28613 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART4 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28646 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART5 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28679 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART6 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28712 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SCRCSTART7 |
[31..16] Start value for polynomial SCD CRC calculation
Definition at line 28745 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS0 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28509 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS1 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28542 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS2 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28575 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS3 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28608 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS4 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28641 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS5 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28674 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS6 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28707 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SELCRCS7 |
[15..15] Selection between polynomial or length for SCD CRC polynomial 0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials 1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
Definition at line 28740 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SINGLEBANK |
[24..24] Use of only one RAM bank for SCD 0: two RAM banks are used for SCD 1: one RAM bank is used for SCD
Definition at line 28807 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SL1 |
[0..0] Current SL line level of channel 1 0: SL line level low 1: SL line level high
Definition at line 29008 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SLAVELOC5 |
[4..4] Slave location 0: slaves 4-7 are connected to channel 1 1: slaves 4-7 are connected to channel 2(only available with iC-MB4 QFN28)
Definition at line 28843 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::status0_reserved1 |
[1..1] reserved value
Definition at line 28867 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID0 |
[9..9] SCDATA0 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28889 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID1 |
[11..11] SCDATA1 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28894 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID2 |
[13..13] SCDATA2 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28899 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID3 |
[15..15] SCDATA3 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28904 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID4 |
[17..17] SCDATA4 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28909 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID5 |
[19..19] SCDATA5 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28914 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID6 |
[21..21] SCDATA6 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28919 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SVALID7 |
[23..23] SCDATA7 validity indication 0: SCD invalid 1: SCD valid The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
Definition at line 28924 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::SWBANK |
[5..5] Switch RAM banks 0: RAM banks are not switched 1: RAM banks are switched
Definition at line 28963 of file netx90_app.h.
| __IM uint32_t biss1_app_Type::SWBANKFAILS |
[24..24] Bank switching status 0: bank switching(SCD) successful 1: bank switching(SCD) not successful
Definition at line 29012 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::VERSION |
[31..24] Device identifier 0x83: iC-MB3 0x84: iC-MB4 .. 0xff
Definition at line 28834 of file netx90_app.h.
| __IOM uint32_t biss1_app_Type::WNR |
[23..23] Register access read/write selector 0: read register data 1: write register data
Definition at line 28755 of file netx90_app.h.
1.8.11