|
| enum | DRV_UART_BAUDRATEMODE_E {
DRV_UART_BAUDRATEMODE_RESET = 0x00u,
DRV_UART_BAUDRATEMODE_0 = 0x01u,
DRV_UART_BAUDRATEMODE_1 = 0x02u,
DRV_UART_BAUDRATEMODE_DEFAULT = DRV_UART_BAUDRATEMODE_1,
DRV_UART_BAUDRATEMODE_MIN = 0x01u,
DRV_UART_BAUDRATEMODE_MAX = 0x02u
} |
| | Enumeration of useful uart baudrate mode. More...
|
| |
| enum | DRV_UART_BAUDRATE_E {
DRV_UART_BAUDRATE_300 = 3ul,
DRV_UART_BAUDRATE_600 = 6ul,
DRV_UART_BAUDRATE_1200 = 12ul,
DRV_UART_BAUDRATE_2400 = 24ul,
DRV_UART_BAUDRATE_4800 = 48ul,
DRV_UART_BAUDRATE_9600 = 96ul,
DRV_UART_BAUDRATE_19200 = 192ul,
DRV_UART_BAUDRATE_38400 = 384ul,
DRV_UART_BAUDRATE_57600 = 576ul,
DRV_UART_BAUDRATE_115200 = 1152ul,
DRV_UART_BAUDRATE_460800 = 4608ul,
DRV_UART_BAUDRATE_DEFAULT = 0
} |
| | Enumeration of useful uart baudrates. More...
|
| |
| enum | DRV_UART_STATE_E {
DRV_UART_STATE_CTS = 0x00000001ul,
DRV_UART_STATE_DSR = 0x00000002ul,
DRV_UART_STATE_DCD = 0x00000004ul,
DRV_UART_STATE_BUSY = 0x00000008ul,
DRV_UART_STATE_RXFE = 0x00000010ul,
DRV_UART_STATE_TXFF = 0x00000020ul,
DRV_UART_STATE_RXFF = 0x00000040ul,
DRV_UART_STATE_TXFE = 0x00000080ul,
DRV_UART_STATE_ERROR_FRAMING = 0x00010000ul,
DRV_UART_STATE_ERROR_PARITY = 0x00020000ul,
DRV_UART_STATE_ERROR_BREAK = 0x00040000ul,
DRV_UART_STATE_ERROR_OVERRUN = 0x00080000ul
} |
| | Enumeration of uart device states. More...
|
| |
| enum | DRV_UART_WORD_LENGTH_E {
DRV_UART_WORD_LENGTH_RESET = 0x00ul,
DRV_UART_WORD_LENGTH_5_BITS = 0x10ul,
DRV_UART_WORD_LENGTH_6_BITS = 0x11ul,
DRV_UART_WORD_LENGTH_7_BITS = 0x12ul,
DRV_UART_WORD_LENGTH_8_BITS = 0x13ul,
DRV_UART_WORD_LENGTH_DEFAULT = DRV_UART_WORD_LENGTH_8_BITS,
DRV_UART_WORD_LENGTH_MIN = DRV_UART_WORD_LENGTH_5_BITS,
DRV_UART_WORD_LENGTH_MAX = DRV_UART_WORD_LENGTH_8_BITS
} |
| | Enumeration of the available uart word lenghts. More...
|
| |
| enum | DRV_UART_LINE_CONTROL_MASK_E {
DRV_UART_LINE_CONTROL_MASK_FIFO_ENABLE = 0x10ul,
DRV_UART_LINE_CONTROL_MASK_ADDITIONAL_STOP_BIT = 0x08ul,
DRV_UART_LINE_CONTROL_MASK_EVEN_PARITY = 0x06ul,
DRV_UART_LINE_CONTROL_MASK_ODD_PARITY = 0x02ul,
DRV_UART_LINE_CONTROL_MASK_SEND_BREAK = 0x01ul,
DRV_UART_LINE_CONTROL_MASK_DEFAULT = 0x00ul,
DRV_UART_LINE_CONTROL_MASK = 0x1ful
} |
| | Enumeration of of the line control parameters as mask. More...
|
| |
| enum | DRV_UART_LOOP_BACK_E {
DRV_UART_LOOP_BACK_INACTIVE = 0x00ul,
DRV_UART_LOOP_BACK_ACTIVE = 0x01ul,
DRV_UART_LOOP_BACK_MAX = DRV_UART_LOOP_BACK_ACTIVE
} |
| | Enumeration of the loop back state. More...
|
| |
| enum | DRV_UART_WATERMARK_E {
DRV_UART_WATERMARK_UNINITIALIZED = 0x00ul,
DRV_UART_WATERMARK_1 = 0x01ul,
DRV_UART_WATERMARK_2 = 0x02ul,
DRV_UART_WATERMARK_3 = 0x03ul,
DRV_UART_WATERMARK_4 = 0x04ul,
DRV_UART_WATERMARK_5 = 0x05ul,
DRV_UART_WATERMARK_6 = 0x06ul,
DRV_UART_WATERMARK_7 = 0x07ul,
DRV_UART_WATERMARK_8 = 0x08ul,
DRV_UART_WATERMARK_DEFAULT = DRV_UART_WATERMARK_8,
DRV_UART_WATERMARK_9 = 0x09ul,
DRV_UART_WATERMARK_10 = 0x0aul,
DRV_UART_WATERMARK_11 = 0x0bul,
DRV_UART_WATERMARK_12 = 0x0cul,
DRV_UART_WATERMARK_13 = 0x0dul,
DRV_UART_WATERMARK_14 = 0x0eul,
DRV_UART_WATERMARK_15 = 0x0ful,
DRV_UART_WATERMARK_16 = 0x10ul,
DRV_UART_WATERMARK_MIN = DRV_UART_WATERMARK_1,
DRV_UART_WATERMARK_MAX = DRV_UART_WATERMARK_16
} |
| | Enumeration of the loop back state. More...
|
| |
| enum | DRV_UART_RTS_CONTROL_MASK_E {
DRV_UART_RTS_CONTROL_MASK_STICK_PARITY = 0x80ul,
DRV_UART_RTS_CONTROL_MASK_CTS_ACTIVE_HIGH = 0x40ul,
DRV_UART_RTS_CONTROL_MASK_CTS_ENABLE = 0x20ul,
DRV_UART_RTS_CONTROL_MASK_RTS_ACTIVE_HIGH = 0x10ul,
DRV_UART_RTS_CONTROL_MASK_ALTERNATIVE_MODE = 0x08ul,
DRV_UART_RTS_CONTROL_MASK_USE_SYSTEM_CLOCK = 0x04ul,
DRV_UART_RTS_CONTROL_MASK_RTS_CONTROL_BIT_SET = 0x02ul,
DRV_UART_RTS_CONTROL_MASK_RTS_AUTOMATIC = 0x01ul,
DRV_UART_RTS_CONTROL_MASK = 0xfful
} |
| | Enumeration of the rts control parameters as mask. More...
|
| |
| enum | DRV_UART_TX_MODE_MASK_E {
DRV_UART_TX_MODE_MASK_DEFAULT = 0x00ul,
DRV_UART_TX_MODE_MASK_RECEIVE_ONLY = 0x01ul,
DRV_UART_TX_MODE_MASK_RTS_ACTIVE = 0x02ul,
DRV_UART_TX_MODE_MASK = 0x03ul
} |
| | Enumeration of the transmit modes availabe as mask. More...
|
| |
peripheral module driver.
- Revision
- 5205
- Date
- 2019-04-17 16:05:00 +0200 (Mi, 17 Apr 2019)
- Copyright
- Copyright (c) Hilscher Gesellschaft fuer Systemautomation mbH. All Rights Reserved.
- Note
- Exclusion of Liability for this demo software: The following software is intended for and must only be used for reference and in an evaluation laboratory environment. It is provided without charge and is subject to alterations. There is no warranty for the software, to the extent permitted by applicable law. Except when otherwise stated in writing the copyright holders and/or other parties provide the software "as is" without warranty of any kind, either expressed or implied. Please refer to the Agreement in README_DISCLAIMER.txt, provided together with this file! By installing or otherwise using the software, you accept the terms of this Agreement. If you do not agree to the terms of this Agreement, then do not install or use the Software!
Definition in file netx_drv_uart.h.
1.8.11