ETH_XPIC module driver. More...

Collaboration diagram for ETH_XPIC:

Data Structures
struct	DRV_ETH_XPIC_CONFIG_T

Macros
#define	HAL_ETHXPIC_VERSION_MAJOR 2

#define	HAL_ETHXPIC_VERSION_MINOR 0

#define	HAL_ETHXPIC_VERSION_BUILD 0

#define	HAL_ETHXPIC_VERSION_REVISION 0

#define	REL_Adr_AREA_ETH_FRAMEBUF_INFO 0x00000000U

#define	REL_Adr_ETH_FRAMEBUF_SIZE 0x00000000U

#define	MSK_ETH_FRAMEBUF_SIZE_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_SIZE_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_SIZE 0xffffffffU

#define	REL_Adr_ETH_FRAMEBUF_INFO 0x00000004U

#define	MSK_ETH_FRAMEBUF_INFO_BUFFER_NUMBER 0x000000ffU

#define	SRT_ETH_FRAMEBUF_INFO_BUFFER_NUMBER 0

#define	MSK_ETH_FRAMEBUF_INFO_CON_EN 0x00000100U

#define	SRT_ETH_FRAMEBUF_INFO_CON_EN 8

#define	MSK_ETH_FRAMEBUF_INFO_MULTIREQ_CNT 0x00000e00U

#define	SRT_ETH_FRAMEBUF_INFO_MULTIREQ_CNT 9

#define	MSK_ETH_FRAMEBUF_INFO_ERROR_CODE 0x00007000U

#define	SRT_ETH_FRAMEBUF_INFO_ERROR_CODE 12

#define	MSK_ETH_FRAMEBUF_INFO_VALID 0x00008000U

#define	SRT_ETH_FRAMEBUF_INFO_VALID 15

#define	MSK_ETH_FRAMEBUF_INFO_RES 0xffff0000U

#define	SRT_ETH_FRAMEBUF_INFO_RES 16

#define	MSK_USED_BITS_ETH_FRAMEBUF_INFO 0xffffffffU

#define	REL_Adr_ETH_FRAMEBUF_STATE 0x00000008U

#define	MSK_ETH_FRAMEBUF_STATE_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_STATE_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_STATE 0xffffffffU

#define	REL_Adr_ETH_FRAMEBUF_ID 0x0000000CU

#define	MSK_ETH_FRAMEBUF_ID_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_ID_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_ID 0xffffffffU

#define	REL_Adr_AREA_ETH_FRAMEBUF_RX_TIMESTAMP 0x00000010U

#define	REL_Adr_ETH_FRAMEBUF_TS_RX_NS 0x00000010U

#define	MSK_ETH_FRAMEBUF_TS_RX_NS_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_TS_RX_NS_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_TS_RX_NS 0xffffffffU

#define	REL_Adr_ETH_FRAMEBUF_TS_RX_S 0x00000014U

#define	MSK_ETH_FRAMEBUF_TS_RX_S_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_TS_RX_S_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_TS_RX_S 0xffffffffU

#define	REL_Adr_AREA_ETH_FRAMEBUF_TX_TIMESTAMP 0x00000018U

#define	REL_Adr_ETH_FRAMEBUF_TS_TX_NS 0x00000018U

#define	MSK_ETH_FRAMEBUF_TS_TX_NS_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_TS_TX_NS_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_TS_TX_NS 0xffffffffU

#define	REL_Adr_ETH_FRAMEBUF_TS_TX_S 0x0000001CU

#define	MSK_ETH_FRAMEBUF_TS_TX_S_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_TS_TX_S_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_TS_TX_S 0xffffffffU

#define	REL_Adr_AREA_ETH_FRAMEBUF_DATA 0x00000020U

#define	REL_Adr_ETH_FRAMEBUF_DATA_START 0x00000020U

#define	MSK_ETH_FRAMEBUF_DATA_START_VAL 0xffffffffU

#define	SRT_ETH_FRAMEBUF_DATA_START_VAL 0

#define	MSK_USED_BITS_ETH_FRAMEBUF_DATA_START 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_CONSTANTPOOL 0x00000000U

#define	REL_Adr_AREA_XPIC_RAM_PARAMETERS 0x00000400U

#define	REL_Adr_XPIC_RAM_SHM_ADDR 0x00000400U

#define	MSK_XPIC_RAM_SHM_ADDR_ADR 0xffffffffU

#define	SRT_XPIC_RAM_SHM_ADDR_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_SHM_ADDR 0xffffffffU

#define	REL_Adr_XPIC_RAM_FRMBUF_ADDR 0x00000404U

#define	MSK_XPIC_RAM_FRMBUF_ADDR_ADR 0xffffffffU

#define	SRT_XPIC_RAM_FRMBUF_ADDR_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_FRMBUF_ADDR 0xffffffffU

#define	REL_Adr_XPIC_RAM_FRAMEBUF_SIZE 0x00000408U

#define	MSK_XPIC_RAM_FRAMEBUF_SIZE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_FRAMEBUF_SIZE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_FRAMEBUF_SIZE 0xffffffffU

#define	REL_Adr_XPIC_RAM_MACADR_HASH_TABLE0 0x0000040CU

#define	MSK_XPIC_RAM_MACADR_HASH_TABLE0_ADR 0xffffffffU

#define	SRT_XPIC_RAM_MACADR_HASH_TABLE0_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE0 0xffffffffU

#define	REL_Adr_XPIC_RAM_MACADR_HASH_TABLE1 0x00000410U

#define	MSK_XPIC_RAM_MACADR_HASH_TABLE1_ADR 0xffffffffU

#define	SRT_XPIC_RAM_MACADR_HASH_TABLE1_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE1 0xffffffffU

#define	REL_Adr_XPIC_RAM_MACADR_HASH_TABLE2 0x00000414U

#define	MSK_XPIC_RAM_MACADR_HASH_TABLE2_RES 0xffffffffU

#define	SRT_XPIC_RAM_MACADR_HASH_TABLE2_RES 0

#define	MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE2 0xffffffffU

#define	REL_Adr_XPIC_RAM_MACADR_HASH_TABLE3 0x00000418U

#define	MSK_XPIC_RAM_MACADR_HASH_TABLE3_RES 0xffffffffU

#define	SRT_XPIC_RAM_MACADR_HASH_TABLE3_RES 0

#define	MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE3 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_IRQ_ADR 0x0000041CU

#define	MSK_XPIC_RAM_RX_IRQ_ADR_ADR 0xffffffffU

#define	SRT_XPIC_RAM_RX_IRQ_ADR_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_RX_IRQ_ADR 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_IRQ_VAL 0x00000420U

#define	MSK_XPIC_RAM_RX_IRQ_VAL_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_IRQ_VAL_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_IRQ_VAL 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_IRQ_ADR 0x00000424U

#define	MSK_XPIC_RAM_TX_IRQ_ADR_ADR 0xffffffffU

#define	SRT_XPIC_RAM_TX_IRQ_ADR_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_TX_IRQ_ADR 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_IRQ_VAL 0x00000428U

#define	MSK_XPIC_RAM_TX_IRQ_VAL_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_IRQ_VAL_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_IRQ_VAL 0xffffffffU

#define	REL_Adr_XPIC_RAM_LOCAL_MAC_ADDRESS_HI 0x0000042CU

#define	MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_HI_VAL 0xffffffffU

#define	SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_HI_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_LOCAL_MAC_ADDRESS_HI 0xffffffffU

#define	REL_Adr_XPIC_RAM_LOCAL_MAC_ADDRESS_LO 0x00000430U

#define	MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_VAL 0x0000ffffU

#define	SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_VAL 0

#define	MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_RES1 0xffff0000U

#define	SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_RES1 16

#define	MSK_USED_BITS_XPIC_RAM_LOCAL_MAC_ADDRESS_LO 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_ABORT_MODE 0x00000434U

#define	MSK_XPIC_RAM_TX_ABORT_MODE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_ABORT_MODE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_ABORT_MODE 0xffffffffU

#define	REL_Adr_XPIC_RAM_ETH_CONFIG 0x00000438U

#define	MSK_XPIC_RAM_ETH_CONFIG_VAL 0xffffffffU

#define	SRT_XPIC_RAM_ETH_CONFIG_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_ETH_CONFIG 0xffffffffU

#define	REL_Adr_XPIC_RAM_ETH_TX_CONFIG 0x0000043CU

#define	MSK_XPIC_RAM_ETH_TX_CONFIG_VAL 0xffffffffU

#define	SRT_XPIC_RAM_ETH_TX_CONFIG_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_ETH_TX_CONFIG 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_REQ_CYCLE 0x00000440U

#define	MSK_XPIC_RAM_MIIMU_REQ_CYCLE_TIME 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_REQ_CYCLE_TIME 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_REQ_CYCLE 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_READ_PHYLINK 0x00000444U

#define	MSK_XPIC_RAM_MIIMU_READ_PHYLINK_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_READ_PHYLINK_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYLINK 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_READ_PHYMODE 0x00000448U

#define	MSK_XPIC_RAM_MIIMU_READ_PHYMODE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_READ_PHYMODE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYMODE 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_READ_PHYSPEED 0x0000044CU

#define	MSK_XPIC_RAM_MIIMU_READ_PHYSPEED_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_READ_PHYSPEED_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYSPEED 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYLINK_MSK 0x00000450U

#define	MSK_XPIC_RAM_PHYLINK_MSK_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYLINK_MSK_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYLINK_MSK 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYMODE_MSK 0x00000454U

#define	MSK_XPIC_RAM_PHYMODE_MSK_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYMODE_MSK_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYMODE_MSK 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYSPEED_MSK 0x00000458U

#define	MSK_XPIC_RAM_PHYSPEED_MSK_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYSPEED_MSK_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYSPEED_MSK 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_LINK_REQ_NXT 0x0000045CU

#define	MSK_XPIC_RAM_MIIMU_LINK_REQ_NXT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_LINK_REQ_NXT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_LINK_REQ_NXT 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_MODE_REQ_NXT 0x00000460U

#define	MSK_XPIC_RAM_MIIMU_MODE_REQ_NXT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_MODE_REQ_NXT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_MODE_REQ_NXT 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_SPEED_REQ_NXT 0x00000464U

#define	MSK_XPIC_RAM_MIIMU_SPEED_REQ_NXT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_SPEED_REQ_NXT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_SPEED_REQ_NXT 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_VAR 0x00000468U

#define	REL_Adr_XPIC_RAM_FRAMEBUF_DATA_SIZE 0x00000468U

#define	MSK_XPIC_RAM_FRAMEBUF_DATA_SIZE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_FRAMEBUF_DATA_SIZE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_FRAMEBUF_DATA_SIZE 0xffffffffU

#define	REL_Adr_XPIC_RAM_FRMBUF_ADDR_NEG 0x0000046CU

#define	MSK_XPIC_RAM_FRMBUF_ADDR_NEG_ADR 0xffffffffU

#define	SRT_XPIC_RAM_FRMBUF_ADDR_NEG_ADR 0

#define	MSK_USED_BITS_XPIC_RAM_FRMBUF_ADDR_NEG 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_PC 0x00000470U

#define	MSK_XPIC_RAM_MIIMU_PC_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_PC_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_PC 0xffffffffU

#define	REL_Adr_XPIC_RAM_MIIMU_REQ_ID 0x00000474U

#define	MSK_XPIC_RAM_MIIMU_REQ_ID_VAL 0xffffffffU

#define	SRT_XPIC_RAM_MIIMU_REQ_ID_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_MIIMU_REQ_ID 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYLINK 0x00000478U

#define	MSK_XPIC_RAM_PHYLINK_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYLINK_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYLINK 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYMODE 0x0000047CU

#define	MSK_XPIC_RAM_PHYMODE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYMODE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYMODE 0xffffffffU

#define	REL_Adr_XPIC_RAM_PHYSPEED 0x00000480U

#define	MSK_XPIC_RAM_PHYSPEED_VAL 0xffffffffU

#define	SRT_XPIC_RAM_PHYSPEED_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_PHYSPEED 0xffffffffU

#define	REL_Adr_XPIC_RAM_SLOT_TIME 0x00000484U

#define	MSK_XPIC_RAM_SLOT_TIME_VAL 0xffffffffU

#define	SRT_XPIC_RAM_SLOT_TIME_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_SLOT_TIME 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_RX_VAR 0x00000488U

#define	REL_Adr_XPIC_RAM_RX_LEN_STAT 0x00000488U

#define	MSK_XPIC_RAM_RX_LEN_STAT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_LEN_STAT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_LEN_STAT 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_FRM_STAT 0x0000048CU

#define	MSK_XPIC_RAM_RX_FRM_STAT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_FRM_STAT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_FRM_STAT 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_FRM_LEN 0x00000490U

#define	MSK_XPIC_RAM_RX_FRM_LEN_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_FRM_LEN_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_FRM_LEN 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_FILL 0x00000494U

#define	MSK_XPIC_RAM_RX_FILL_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_FILL_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_FILL 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_OFS_IP_DATA 0x00000498U

#define	MSK_XPIC_RAM_RX_OFS_IP_DATA_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_OFS_IP_DATA_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_OFS_IP_DATA 0xffffffffU

#define	REL_Adr_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT 0x0000049CU

#define	MSK_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_RX_BUF 0x000004A0U

#define	REL_Adr_AREA_XPIC_RAM_RX_ERR_TAB 0x000005A0U

#define	REL_Adr_AREA_XPIC_RAM_RX_FRWD_FIFO_TAB 0x000005B0U

#define	REL_Adr_AREA_XPIC_RAM_RX_IRQ_MSK_TAB 0x000005C0U

#define	REL_Adr_AREA_XPIC_RAM_IRQ_STACK 0x000005D0U

#define	REL_Adr_XPIC_RAM_IRQ_STACK_PC 0x000005D0U

#define	MSK_XPIC_RAM_IRQ_STACK_PC_VAL 0xffffffffU

#define	SRT_XPIC_RAM_IRQ_STACK_PC_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_IRQ_STACK_PC 0xffffffffU

#define	REL_Adr_XPIC_RAM_IRQ_STACK_STAT 0x000005D4U

#define	MSK_XPIC_RAM_IRQ_STACK_STAT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_IRQ_STACK_STAT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_IRQ_STACK_STAT 0xffffffffU

#define	REL_Adr_XPIC_RAM_IRQ_STACK_R0 0x000005D8U

#define	MSK_XPIC_RAM_IRQ_STACK_R0_VAL 0xffffffffU

#define	SRT_XPIC_RAM_IRQ_STACK_R0_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_IRQ_STACK_R0 0xffffffffU

#define	REL_Adr_XPIC_RAM_IRQ_STACK_REQ_HOST 0x000005DCU

#define	MSK_XPIC_RAM_IRQ_STACK_REQ_HOST_VAL 0xffffffffU

#define	SRT_XPIC_RAM_IRQ_STACK_REQ_HOST_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_IRQ_STACK_REQ_HOST 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_TX_VAR 0x000005E0U

#define	REL_Adr_XPIC_RAM_TX_STATE_PC 0x000005E0U

#define	MSK_XPIC_RAM_TX_STATE_PC_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_STATE_PC_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_STATE_PC 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FINISH_PC 0x000005E4U

#define	MSK_XPIC_RAM_TX_FINISH_PC_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FINISH_PC_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FINISH_PC 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_LENGTH 0x000005E8U

#define	MSK_XPIC_RAM_TX_LENGTH_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_LENGTH_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_LENGTH 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_LENGTH_WRITTEN 0x000005ECU

#define	MSK_XPIC_RAM_TX_LENGTH_WRITTEN_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_LENGTH_WRITTEN_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_LENGTH_WRITTEN 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT 0x000005F0U

#define	MSK_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_RETRY 0x000005F4U

#define	MSK_XPIC_RAM_TX_RETRY_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_RETRY_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_RETRY 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_FREE 0x000005F8U

#define	MSK_XPIC_RAM_TX_FOLLOW_FREE_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_FREE_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_FREE 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_BUF 0x000005FCU

#define	MSK_XPIC_RAM_TX_FOLLOW_BUF_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_BUF_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_BUF 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_DLR 0x00000600U

#define	MSK_XPIC_RAM_TX_FOLLOW_DLR_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_DLR_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_DLR 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_HI 0x00000604U

#define	MSK_XPIC_RAM_TX_FOLLOW_HI_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_HI_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_HI 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_LO 0x00000608U

#define	MSK_XPIC_RAM_TX_FOLLOW_LO_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_LO_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_LO 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_FOLLOW_FRAME 0x0000060CU

#define	MSK_XPIC_RAM_TX_FOLLOW_FRAME_VAL 0xffffffffU

#define	SRT_XPIC_RAM_TX_FOLLOW_FRAME_VAL 0

#define	MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_FRAME 0xffffffffU

#define	REL_Adr_AREA_XPIC_RAM_TX_SND_TAB 0x00000610U

#define	REL_Adr_AREA_XPIC_RAM_RESERVED 0x00000624U

#define	REL_Adr_XPIC_RAM_RX_STATE 0x00000624U

#define	MSK_XPIC_RAM_RX_STATE_DROPPED 0x00000001U

#define	SRT_XPIC_RAM_RX_STATE_DROPPED 0

#define	MSK_XPIC_RAM_RX_STATE_FINISH 0x00000002U

#define	SRT_XPIC_RAM_RX_STATE_FINISH 1

#define	MSK_XPIC_RAM_RX_STATE_PRIO_HI 0x00000004U

#define	SRT_XPIC_RAM_RX_STATE_PRIO_HI 2

#define	MSK_XPIC_RAM_RX_STATE_PRIO_RT 0x00000008U

#define	SRT_XPIC_RAM_RX_STATE_PRIO_RT 3

#define	MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT0 0x00000010U

#define	SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT0 4

#define	MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT1 0x00000020U

#define	SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT1 5

#define	MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT2 0x00000040U

#define	SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT2 6

#define	MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT3 0x00000080U

#define	SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT3 7

#define	MSK_XPIC_RAM_RX_STATE_VLAN_TAG 0x00000100U

#define	SRT_XPIC_RAM_RX_STATE_VLAN_TAG 8

#define	MSK_XPIC_RAM_RX_STATE_IP_PACKET 0x00000200U

#define	SRT_XPIC_RAM_RX_STATE_IP_PACKET 9

#define	MSK_XPIC_RAM_RX_STATE_DATA_PARSED 0x00000400U

#define	SRT_XPIC_RAM_RX_STATE_DATA_PARSED 10

#define	MSK_XPIC_RAM_RX_STATE_FORWARDED 0x00000800U

#define	SRT_XPIC_RAM_RX_STATE_FORWARDED 11

#define	MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_LOCAL_PORT 0x00001000U

#define	SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_LOCAL_PORT 12

#define	MSK_XPIC_RAM_RX_STATE_RES1 0xffffe000U

#define	SRT_XPIC_RAM_RX_STATE_RES1 13

#define	MSK_USED_BITS_XPIC_RAM_RX_STATE 0xffffffffU

#define	REL_Adr_XPIC_RAM_TX_STATE 0x00000628U

#define	MSK_XPIC_RAM_TX_STATE_ACTIVE 0x00000001U

#define	SRT_XPIC_RAM_TX_STATE_ACTIVE 0

#define	MSK_XPIC_RAM_TX_STATE_RES1 0xfffffffeU

#define	SRT_XPIC_RAM_TX_STATE_RES1 1

#define	MSK_USED_BITS_XPIC_RAM_TX_STATE 0xffffffffU

#define	HAL_ETH_STD_MAC_XPIC_TARGET_NX90_APP

#define	_HW_CONCAT(a, b) a ## b

#define	HW_MSK(bf) _HW_CONCAT(MSK_NX90_, bf)

#define	HW_SRT(bf) _HW_CONCAT(SRT_NX90_, bf)

#define	HW_DFLT_BF_VAL(bf) _HW_CONCAT(DFLT_BF_VAL_NX90_, bf)

#define	HW_DFLT_VAL(reg) _HW_CONCAT(DFLT_VAL_NX90_, reg)

#define	HW_REGADR(reg) _HW_CONCAT(Adr_NX90_, reg)

#define	HW_AREAADR(area) _HW_CONCAT(Addr_NX90_, area)

#define	HW_TYPE(area) _HW_CONCAT(NX90_, area)

#define	NX_WRITE32(var, val) (var) = (val)

#define	NX_READ32(var) (var)

#define	NX_WRITE16(var, val) (var) = (val)

#define	NX_READ16(var) (var)

#define	NX_WRITE8(var, val) (var) = (val)

#define	NX_READ8(var) (var)

#define	NX_READMEM(dst, src, len) memcpy(dst, src, len)

#define	NX_WRITEMEM(dst, src, len) memcpy(dst, src, len)

#define	XcCode_eth_xpic_prg1 XpicCode_eth_xpic_prg1

#define	PrgSiz_eth_xpic_prg1 XpicCode_eth_xpic_prg1[0]

#define	TrlSiz_eth_xpic_prg1 XpicCode_eth_xpic_prg1[1]

#define	PrgSrt_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[2]

#define	PrgStp_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[3]

#define	TrlSrt_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[3]

#define	TrlStp_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[1797]

#define	ETH_XPIC_INST 0

#define	ETH_XPIC_PRG XpicCode_eth_xpic_prg1

#define	ETH_XPIC_ARMIRQ_ADR Adr_NX90_mcp_xpic_app_hs_irq_set_raw

#define	ETH_XPIC_ARMIRQ_VAL 0x00100000

#define	ETH_XPIC_SHM_BASE Addr_NX90_intram7

#define	ETH_XPIC_DFLT_TX_OUTPUT_PHASE 3 /* PosEdge + 5cc */

#define	OFS_ETH_XPIC_SHM_AREA 0

#define	ADR_ETH_XPIC_SHM_AREA (ETH_XPIC_SHM_BASE + OFS_ETH_XPIC_SHM_AREA)

#define	ADR_ETH_XPIC_FRAME_BUFFER_AREA (ADR_ETH_XPIC_SHM_AREA + sizeof(ETH_XPIC_SHM_T))

#define	HOSTPTR_ETH_XPIC_SHM_AREA (ETH_XPIC_SHM_BASE + OFS_ETH_XPIC_SHM_AREA)

#define	HOSTPTR_ETH_XPIC_FRAME_BUFFER_AREA (HOSTPTR_ETH_XPIC_SHM_AREA + sizeof(ETH_XPIC_SHM_T))

#define	ETH_XPIC_FRAME_BUFFER_AREA_SIZE (0x8000 - sizeof(ETH_XPIC_SHM_T) - OFS_ETH_XPIC_SHM_AREA)

#define	ETH_XPIC_FRAMEBUF_CNT (ETH_XPIC_FRAME_BUFFER_AREA_SIZE / ETH_XPIC_FRAME_BUFFER_SIZE)

#define	ETH_XPIC_TX_OUTPUT_PHASE ETH_XPIC_DFLT_TX_OUTPUT_PHASE

#define	XC_INTRAM_START_ADDRESS 0

#define	ETH_XPIC_MIIM_LINK_STATUS_REG 1

#define	ETH_XPIC_MIIM_LINK_STATUS_BIT 2

#define	ETH_XPIC_MIIM_REQ_LINK 0

#define	ETH_XPIC_MIIM_REQ_MODE 1

#define	ETH_XPIC_MIIM_REQ_SPEED 2

#define	ETH_XPIC_ETH_CFG_PHYMODE (HW_MSK(eth_config_rx_systime_sfd) \| HW_MSK(eth_config_phy_mode))

#define	ETH_XPIC_ETH_CFG_MACMODE (HW_MSK(eth_config_rx_systime_sfd) \| HW_MSK(eth_config_rx_delay_inputs))

#define	ETH_XPIC_ETH_TX_CFG_FD

#define	ETH_XPIC_ETH_TX_CFG_HD (ETH_XPIC_ETH_TX_CFG_FD \| HW_MSK(eth_tx_config_half_duplex))

#define	ETH_XPIC_PFIFO_DEPTH (sizeof(XPIC_SHM_PFIFO_EMPTY_PTR_T))

#define	ETH_XPIC_PFIFO_BORDER (ETH_XPIC_PFIFO_DEPTH - 1U)

#define	HOSTPTR_ETH_XPIC_FRAME_BUFFER(elem) (HOSTPTR_ETH_XPIC_FRAME_BUFFER_AREA + elem * ETH_XPIC_FRAME_BUFFER_SIZE)

#define	MIIMU_SRT(bf) HW_SRT(_HW_CONCAT(miimu_, bf))

#define	MIIMU_MSK(bf) HW_MSK(_HW_CONCAT(miimu_, bf))

Enumerations
enum	DRV_ETH_XPIC_RESULT { DRV_ETH_XPIC_OK = 0, DRV_ETH_XPIC_NOT_INITIALIZED, DRV_ETH_XPIC_NOT_RUNNING, DRV_ETH_XPIC_INVALID_ARG, DRV_ETH_XPIC_NO_FRAME_AVAILABLE, DRV_ETH_XPIC_INVALID_HANDLE }

enum	DRV_ETH_XPIC_PARAM { DRV_ETH_XPIC_PARAM_IRQ_MASK = 0, DRV_ETH_XPIC_PARAM_VLAN_PRIORITIZATION, DRV_ETH_XPIC_PARAM_DSCP_PRIORITIZATION, DRV_ETH_XPIC_PROMISC_MODE, DRV_ETH_XPIC_CONNECTION_STATE }

enum	DRV_ETH_XPIC_STATE { DRV_ETH_XPIC_STATE_UNDEF = 0, DRV_ETH_XPIC_STATE_RESET, DRV_ETH_XPIC_STATE_INITIALIZED, DRV_ETH_XPIC_STATE_RUNNING }

Functions
DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_Reset (void *pvUser)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_Initialize (DRV_ETH_XPIC_CONFIG_T const ptConfig, void pvUser)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_SetMacAddr (uint8_t const *pabMacAdr)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetMacAddr (uint8_t *pabMacAdr)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_Start (void *pvUser)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetConfirmIrq (uint32_t *pulIrq)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetFrame (ETH_FRAMEBUF_T **pptFrame)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_Send (ETH_FRAMEBUF_T *ptFrame, bool fConfirm, bool fHiPriority)

unsigned int	DRV_ETH_Xpic_GetSendCnfFillLevel (void)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetSendCnf (ETH_FRAMEBUF_T *pptFrame, ETH_XPIC_CNF_ERR pErrorCode)

unsigned int	DRV_ETH_Xpic_GetRecvFillLevel (bool fHiPriority)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_Recv (ETH_FRAMEBUF_T **pptFrame, bool fHiPriority)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_ReleaseFrame (ETH_FRAMEBUF_T *ptFrame)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_SetParam (DRV_ETH_XPIC_PARAM eParam, uint32_t ulValue)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetParam (DRV_ETH_XPIC_PARAM eParam, uint32_t *pulValue)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_GetCounters (XPIC_SHM_CNT_T *ptMacCounter)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_ReadPhyReg (unsigned int uMiimuPreamble, unsigned int uMiimuMdcFreq, unsigned int uMiimuRtaField, unsigned int uMiimuPhyAddr, unsigned int uMiimuReqAddr, uint16_t pusData, void pvUser)

DRV_ETH_XPIC_RESULT	DRV_ETH_Xpic_WritePhyReg (unsigned int uMiimuPreamble, unsigned int uMiimuMdcFreq, unsigned int uMiimuPhyAddr, unsigned int uMiimuReqAddr, uint16_t usData, void *pvUser)

Variables
const uint32_t	BuildTime_eth_xpic_prg1 [7] = { 53, 55, 6, 3, 8, 119, 1567493753 }

const uint32_t	XpicCode_eth_xpic_prg1 [1797]

static uint32_t *const	s_apulXpicDram [] = { (uint32_t*) Addr_NX90_xpic_app_dram }

static volatile DRV_ETH_XPIC_STATE	s_eState = DRV_ETH_XPIC_STATE_UNDEF

static uint8_t	s_abMacAdr [6] = { 0, 1, 2, 3, 4, 5 }

static ETH_XPIC_SHM_AREA_T *	s_ptXpicShm = NULL

Detailed Description

ETH_XPIC module driver.

This driver is one of our legacy HALs. The support for the legacy hall's is very limited. They are developed and maintained by our chip development and verification department and provide only a hardware near abstraction layer. They are in most cases not convenient or do not support as much functionality as that

Macro Definition Documentation

#define _HW_CONCAT	(	a,
		b
	)	a ## b

Definition at line 52 of file netx_drv_eth_xpic.c.

#define ADR_ETH_XPIC_FRAME_BUFFER_AREA (ADR_ETH_XPIC_SHM_AREA + sizeof(ETH_XPIC_SHM_T))

Definition at line 132 of file netx_drv_eth_xpic.c.

#define ADR_ETH_XPIC_SHM_AREA (ETH_XPIC_SHM_BASE + OFS_ETH_XPIC_SHM_AREA)

Definition at line 127 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ARMIRQ_ADR Adr_NX90_mcp_xpic_app_hs_irq_set_raw

Definition at line 92 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ARMIRQ_VAL 0x00100000

Definition at line 93 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_DFLT_TX_OUTPUT_PHASE 3 /* PosEdge + 5cc */

Definition at line 95 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ETH_CFG_MACMODE (HW_MSK(eth_config_rx_systime_sfd) | HW_MSK(eth_config_rx_delay_inputs))

Definition at line 171 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ETH_CFG_PHYMODE (HW_MSK(eth_config_rx_systime_sfd) | HW_MSK(eth_config_phy_mode))

Definition at line 170 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ETH_TX_CFG_FD

Value:

(1  << HW_SRT(eth_tx_config_tx_systime_sfd))\
  |(1  << HW_SRT(eth_tx_config_tx_watermark_start))\
  |(16 << HW_SRT(eth_tx_config_tx_preamble_len))\
  |(24 << HW_SRT(eth_tx_config_tx_min_ifg_cycles))\
  |(16 << HW_SRT(eth_tx_config_tx_crs_low_cycles))\
  |(ETH_XPIC_TX_OUTPUT_PHASE << HW_SRT(eth_tx_config_tx_output_phase))

Definition at line 172 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_ETH_TX_CFG_HD (ETH_XPIC_ETH_TX_CFG_FD | HW_MSK(eth_tx_config_half_duplex))

Definition at line 178 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_FRAME_BUFFER_AREA_SIZE (0x8000 - sizeof(ETH_XPIC_SHM_T) - OFS_ETH_XPIC_SHM_AREA)

Definition at line 147 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_FRAMEBUF_CNT (ETH_XPIC_FRAME_BUFFER_AREA_SIZE / ETH_XPIC_FRAME_BUFFER_SIZE)

Definition at line 152 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_INST 0

Definition at line 90 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_MIIM_LINK_STATUS_BIT 2

Definition at line 164 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_MIIM_LINK_STATUS_REG 1

Definition at line 163 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_MIIM_REQ_LINK 0

Definition at line 166 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_MIIM_REQ_MODE 1

Definition at line 167 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_MIIM_REQ_SPEED 2

Definition at line 168 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_PFIFO_BORDER (ETH_XPIC_PFIFO_DEPTH - 1U)

Definition at line 181 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_PFIFO_DEPTH (sizeof(XPIC_SHM_PFIFO_EMPTY_PTR_T))

Definition at line 180 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_PRG XpicCode_eth_xpic_prg1

Definition at line 91 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_SHM_BASE Addr_NX90_intram7

Definition at line 94 of file netx_drv_eth_xpic.c.

#define ETH_XPIC_TX_OUTPUT_PHASE ETH_XPIC_DFLT_TX_OUTPUT_PHASE

Definition at line 157 of file netx_drv_eth_xpic.c.

#define HAL_ETH_STD_MAC_XPIC_TARGET_NX90_APP

Definition at line 46 of file netx_drv_eth_xpic.c.

#define HAL_ETHXPIC_VERSION_BUILD 0

Definition at line 46 of file netx_drv_eth_xpic.h.

#define HAL_ETHXPIC_VERSION_MAJOR 2

Definition at line 44 of file netx_drv_eth_xpic.h.

#define HAL_ETHXPIC_VERSION_MINOR 0

Definition at line 45 of file netx_drv_eth_xpic.h.

#define HAL_ETHXPIC_VERSION_REVISION 0

Definition at line 47 of file netx_drv_eth_xpic.h.

#define HOSTPTR_ETH_XPIC_FRAME_BUFFER ( elem ) (HOSTPTR_ETH_XPIC_FRAME_BUFFER_AREA + elem * ETH_XPIC_FRAME_BUFFER_SIZE)

Definition at line 183 of file netx_drv_eth_xpic.c.

#define HOSTPTR_ETH_XPIC_FRAME_BUFFER_AREA (HOSTPTR_ETH_XPIC_SHM_AREA + sizeof(ETH_XPIC_SHM_T))

Definition at line 142 of file netx_drv_eth_xpic.c.

#define HOSTPTR_ETH_XPIC_SHM_AREA (ETH_XPIC_SHM_BASE + OFS_ETH_XPIC_SHM_AREA)

Definition at line 137 of file netx_drv_eth_xpic.c.

#define HW_AREAADR ( area ) _HW_CONCAT(Addr_NX90_, area)

Definition at line 58 of file netx_drv_eth_xpic.c.

#define HW_DFLT_BF_VAL ( bf ) _HW_CONCAT(DFLT_BF_VAL_NX90_, bf)

Definition at line 55 of file netx_drv_eth_xpic.c.

#define HW_DFLT_VAL ( reg ) _HW_CONCAT(DFLT_VAL_NX90_, reg)

Definition at line 56 of file netx_drv_eth_xpic.c.

#define HW_MSK ( bf ) _HW_CONCAT(MSK_NX90_, bf)

Definition at line 53 of file netx_drv_eth_xpic.c.

#define HW_REGADR ( reg ) _HW_CONCAT(Adr_NX90_, reg)

Definition at line 57 of file netx_drv_eth_xpic.c.

#define HW_SRT ( bf ) _HW_CONCAT(SRT_NX90_, bf)

Definition at line 54 of file netx_drv_eth_xpic.c.

#define HW_TYPE ( area ) _HW_CONCAT(NX90_, area)

Definition at line 59 of file netx_drv_eth_xpic.c.

#define MIIMU_MSK ( bf ) HW_MSK(_HW_CONCAT(miimu_, bf))

Definition at line 187 of file netx_drv_eth_xpic.c.

#define MIIMU_SRT ( bf ) HW_SRT(_HW_CONCAT(miimu_, bf))

Definition at line 186 of file netx_drv_eth_xpic.c.

#define MSK_ETH_FRAMEBUF_DATA_START_VAL 0xffffffffU

Definition at line 212 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_ID_VAL 0xffffffffU

Definition at line 118 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_BUFFER_NUMBER 0x000000ffU

Definition at line 80 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_CON_EN 0x00000100U

Definition at line 82 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_ERROR_CODE 0x00007000U

Definition at line 86 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_MULTIREQ_CNT 0x00000e00U

Definition at line 84 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_RES 0xffff0000U

Definition at line 90 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_INFO_VALID 0x00008000U

Definition at line 88 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_SIZE_VAL 0xffffffffU

Definition at line 66 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_STATE_VAL 0xffffffffU

Definition at line 104 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_TS_RX_NS_VAL 0xffffffffU

Definition at line 140 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_TS_RX_S_VAL 0xffffffffU

Definition at line 154 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_TS_TX_NS_VAL 0xffffffffU

Definition at line 176 of file netx_drv_eth_xpic_def.h.

#define MSK_ETH_FRAMEBUF_TS_TX_S_VAL 0xffffffffU

Definition at line 190 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_DATA_START 0xffffffffU

Definition at line 216 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_ID 0xffffffffU

Definition at line 122 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_INFO 0xffffffffU

Definition at line 94 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_SIZE 0xffffffffU

Definition at line 70 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_STATE 0xffffffffU

Definition at line 108 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_TS_RX_NS 0xffffffffU

Definition at line 144 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_TS_RX_S 0xffffffffU

Definition at line 158 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_TS_TX_NS 0xffffffffU

Definition at line 180 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_ETH_FRAMEBUF_TS_TX_S 0xffffffffU

Definition at line 194 of file netx_drv_eth_xpic_def.h.

#define MSK_USED_BITS_XPIC_RAM_ETH_CONFIG 0xffffffffU

Definition at line 281 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_ETH_TX_CONFIG 0xffffffffU

Definition at line 295 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_FRAMEBUF_DATA_SIZE 0xffffffffU

Definition at line 457 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_FRAMEBUF_SIZE 0xffffffffU

Definition at line 111 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_FRMBUF_ADDR 0xffffffffU

Definition at line 97 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_FRMBUF_ADDR_NEG 0xffffffffU

Definition at line 471 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_IRQ_STACK_PC 0xffffffffU

Definition at line 701 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_IRQ_STACK_R0 0xffffffffU

Definition at line 729 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_IRQ_STACK_REQ_HOST 0xffffffffU

Definition at line 743 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_IRQ_STACK_STAT 0xffffffffU

Definition at line 715 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_LOCAL_MAC_ADDRESS_HI 0xffffffffU

Definition at line 237 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_LOCAL_MAC_ADDRESS_LO 0xffffffffU

Definition at line 253 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE0 0xffffffffU

Definition at line 125 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE1 0xffffffffU

Definition at line 139 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE2 0xffffffffU

Definition at line 153 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MACADR_HASH_TABLE3 0xffffffffU

Definition at line 167 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_LINK_REQ_NXT 0xffffffffU

Definition at line 407 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_MODE_REQ_NXT 0xffffffffU

Definition at line 421 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_PC 0xffffffffU

Definition at line 485 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYLINK 0xffffffffU

Definition at line 323 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYMODE 0xffffffffU

Definition at line 337 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_READ_PHYSPEED 0xffffffffU

Definition at line 351 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_REQ_CYCLE 0xffffffffU

Definition at line 309 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_REQ_ID 0xffffffffU

Definition at line 499 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_MIIMU_SPEED_REQ_NXT 0xffffffffU

Definition at line 435 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYLINK 0xffffffffU

Definition at line 513 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYLINK_MSK 0xffffffffU

Definition at line 365 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYMODE 0xffffffffU

Definition at line 527 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYMODE_MSK 0xffffffffU

Definition at line 379 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYSPEED 0xffffffffU

Definition at line 541 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_PHYSPEED_MSK 0xffffffffU

Definition at line 393 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_FILL 0xffffffffU

Definition at line 619 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT 0xffffffffU

Definition at line 647 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_FRM_LEN 0xffffffffU

Definition at line 605 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_FRM_STAT 0xffffffffU

Definition at line 591 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_IRQ_ADR 0xffffffffU

Definition at line 181 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_IRQ_VAL 0xffffffffU

Definition at line 195 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_LEN_STAT 0xffffffffU

Definition at line 577 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_OFS_IP_DATA 0xffffffffU

Definition at line 633 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_RX_STATE 0xffffffffU

Definition at line 975 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_SHM_ADDR 0xffffffffU

Definition at line 83 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_SLOT_TIME 0xffffffffU

Definition at line 555 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_ABORT_MODE 0xffffffffU

Definition at line 267 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FINISH_PC 0xffffffffU

Definition at line 779 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_BUF 0xffffffffU

Definition at line 863 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_DLR 0xffffffffU

Definition at line 877 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_FRAME 0xffffffffU

Definition at line 919 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_FREE 0xffffffffU

Definition at line 849 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_HI 0xffffffffU

Definition at line 891 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FOLLOW_LO 0xffffffffU

Definition at line 905 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT 0xffffffffU

Definition at line 821 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_IRQ_ADR 0xffffffffU

Definition at line 209 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_IRQ_VAL 0xffffffffU

Definition at line 223 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_LENGTH 0xffffffffU

Definition at line 793 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_LENGTH_WRITTEN 0xffffffffU

Definition at line 807 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_RETRY 0xffffffffU

Definition at line 835 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_STATE 0xffffffffU

Definition at line 991 of file netx_drv_eth_xpic_ram.h.

#define MSK_USED_BITS_XPIC_RAM_TX_STATE_PC 0xffffffffU

Definition at line 765 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_ETH_CONFIG_VAL 0xffffffffU

Definition at line 277 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_ETH_TX_CONFIG_VAL 0xffffffffU

Definition at line 291 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_FRAMEBUF_DATA_SIZE_VAL 0xffffffffU

Definition at line 453 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_FRAMEBUF_SIZE_VAL 0xffffffffU

Definition at line 107 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_FRMBUF_ADDR_ADR 0xffffffffU

Definition at line 93 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_FRMBUF_ADDR_NEG_ADR 0xffffffffU

Definition at line 467 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_IRQ_STACK_PC_VAL 0xffffffffU

Definition at line 697 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_IRQ_STACK_R0_VAL 0xffffffffU

Definition at line 725 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_IRQ_STACK_REQ_HOST_VAL 0xffffffffU

Definition at line 739 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_IRQ_STACK_STAT_VAL 0xffffffffU

Definition at line 711 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_HI_VAL 0xffffffffU

Definition at line 233 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_RES1 0xffff0000U

Definition at line 249 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_VAL 0x0000ffffU

Definition at line 247 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MACADR_HASH_TABLE0_ADR 0xffffffffU

Definition at line 121 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MACADR_HASH_TABLE1_ADR 0xffffffffU

Definition at line 135 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MACADR_HASH_TABLE2_RES 0xffffffffU

Definition at line 149 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MACADR_HASH_TABLE3_RES 0xffffffffU

Definition at line 163 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_LINK_REQ_NXT_VAL 0xffffffffU

Definition at line 403 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_MODE_REQ_NXT_VAL 0xffffffffU

Definition at line 417 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_PC_VAL 0xffffffffU

Definition at line 481 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_READ_PHYLINK_VAL 0xffffffffU

Definition at line 319 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_READ_PHYMODE_VAL 0xffffffffU

Definition at line 333 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_READ_PHYSPEED_VAL 0xffffffffU

Definition at line 347 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_REQ_CYCLE_TIME 0xffffffffU

Definition at line 305 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_REQ_ID_VAL 0xffffffffU

Definition at line 495 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_MIIMU_SPEED_REQ_NXT_VAL 0xffffffffU

Definition at line 431 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYLINK_MSK_VAL 0xffffffffU

Definition at line 361 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYLINK_VAL 0xffffffffU

Definition at line 509 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYMODE_MSK_VAL 0xffffffffU

Definition at line 375 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYMODE_VAL 0xffffffffU

Definition at line 523 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYSPEED_MSK_VAL 0xffffffffU

Definition at line 389 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_PHYSPEED_VAL 0xffffffffU

Definition at line 537 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_FILL_VAL 0xffffffffU

Definition at line 615 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT_VAL 0xffffffffU

Definition at line 643 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_FRM_LEN_VAL 0xffffffffU

Definition at line 601 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_FRM_STAT_VAL 0xffffffffU

Definition at line 587 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_IRQ_ADR_ADR 0xffffffffU

Definition at line 177 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_IRQ_VAL_VAL 0xffffffffU

Definition at line 191 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_LEN_STAT_VAL 0xffffffffU

Definition at line 573 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_OFS_IP_DATA_VAL 0xffffffffU

Definition at line 629 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_DATA_PARSED 0x00000400U

Definition at line 965 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_DROPPED 0x00000001U

Definition at line 945 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FINISH 0x00000002U

Definition at line 947 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FORWARDED 0x00000800U

Definition at line 967 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_LOCAL_PORT 0x00001000U

Definition at line 969 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT0 0x00000010U

Definition at line 953 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT1 0x00000020U

Definition at line 955 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT2 0x00000040U

Definition at line 957 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT3 0x00000080U

Definition at line 959 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_IP_PACKET 0x00000200U

Definition at line 963 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_PRIO_HI 0x00000004U

Definition at line 949 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_PRIO_RT 0x00000008U

Definition at line 951 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_RES1 0xffffe000U

Definition at line 971 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_RX_STATE_VLAN_TAG 0x00000100U

Definition at line 961 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_SHM_ADDR_ADR 0xffffffffU

Definition at line 79 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_SLOT_TIME_VAL 0xffffffffU

Definition at line 551 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_ABORT_MODE_VAL 0xffffffffU

Definition at line 263 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FINISH_PC_VAL 0xffffffffU

Definition at line 775 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_BUF_VAL 0xffffffffU

Definition at line 859 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_DLR_VAL 0xffffffffU

Definition at line 873 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_FRAME_VAL 0xffffffffU

Definition at line 915 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_FREE_VAL 0xffffffffU

Definition at line 845 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_HI_VAL 0xffffffffU

Definition at line 887 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FOLLOW_LO_VAL 0xffffffffU

Definition at line 901 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT_VAL 0xffffffffU

Definition at line 817 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_IRQ_ADR_ADR 0xffffffffU

Definition at line 205 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_IRQ_VAL_VAL 0xffffffffU

Definition at line 219 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_LENGTH_VAL 0xffffffffU

Definition at line 789 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_LENGTH_WRITTEN_VAL 0xffffffffU

Definition at line 803 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_RETRY_VAL 0xffffffffU

Definition at line 831 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_STATE_ACTIVE 0x00000001U

Definition at line 985 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_STATE_PC_VAL 0xffffffffU

Definition at line 761 of file netx_drv_eth_xpic_ram.h.

#define MSK_XPIC_RAM_TX_STATE_RES1 0xfffffffeU

Definition at line 987 of file netx_drv_eth_xpic_ram.h.

#define NX_READ16 ( var ) (var)

Definition at line 65 of file netx_drv_eth_xpic.c.

#define NX_READ32 ( var ) (var)

Definition at line 63 of file netx_drv_eth_xpic.c.

#define NX_READ8 ( var ) (var)

Definition at line 67 of file netx_drv_eth_xpic.c.

#define NX_READMEM	(	dst,
		src,
		len
	)	memcpy(dst, src, len)

Definition at line 69 of file netx_drv_eth_xpic.c.

#define NX_WRITE16	(	var,
		val
	)	(var) = (val)

Definition at line 64 of file netx_drv_eth_xpic.c.

#define NX_WRITE32	(	var,
		val
	)	(var) = (val)

Definition at line 62 of file netx_drv_eth_xpic.c.

#define NX_WRITE8	(	var,
		val
	)	(var) = (val)

Definition at line 66 of file netx_drv_eth_xpic.c.

#define NX_WRITEMEM	(	dst,
		src,
		len
	)	memcpy(dst, src, len)

Definition at line 71 of file netx_drv_eth_xpic.c.

#define OFS_ETH_XPIC_SHM_AREA 0

Definition at line 122 of file netx_drv_eth_xpic.c.

#define PrgSiz_eth_xpic_prg1 XpicCode_eth_xpic_prg1[0]

Definition at line 81 of file netx_drv_eth_xpic.c.

#define PrgSrt_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[2]

Definition at line 84 of file netx_drv_eth_xpic.c.

#define PrgStp_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[3]

Definition at line 85 of file netx_drv_eth_xpic.c.

#define REL_Adr_AREA_ETH_FRAMEBUF_DATA 0x00000020U

Definition at line 202 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_AREA_ETH_FRAMEBUF_INFO 0x00000000U

Definition at line 56 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_AREA_ETH_FRAMEBUF_RX_TIMESTAMP 0x00000010U

Definition at line 130 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_AREA_ETH_FRAMEBUF_TX_TIMESTAMP 0x00000018U

Definition at line 166 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_AREA_XPIC_RAM_CONSTANTPOOL 0x00000000U

Definition at line 61 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_IRQ_STACK 0x000005D0U

Definition at line 687 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_PARAMETERS 0x00000400U

Definition at line 69 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RESERVED 0x00000624U

Definition at line 935 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RX_BUF 0x000004A0U

Definition at line 655 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RX_ERR_TAB 0x000005A0U

Definition at line 663 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RX_FRWD_FIFO_TAB 0x000005B0U

Definition at line 671 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RX_IRQ_MSK_TAB 0x000005C0U

Definition at line 679 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_RX_VAR 0x00000488U

Definition at line 563 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_TX_SND_TAB 0x00000610U

Definition at line 927 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_TX_VAR 0x000005E0U

Definition at line 751 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_AREA_XPIC_RAM_VAR 0x00000468U

Definition at line 443 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_ETH_FRAMEBUF_DATA_START 0x00000020U

Definition at line 210 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_ID 0x0000000CU

Definition at line 116 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_INFO 0x00000004U

Definition at line 78 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_SIZE 0x00000000U

Definition at line 64 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_STATE 0x00000008U

Definition at line 102 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_TS_RX_NS 0x00000010U

Definition at line 138 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_TS_RX_S 0x00000014U

Definition at line 152 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_TS_TX_NS 0x00000018U

Definition at line 174 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_ETH_FRAMEBUF_TS_TX_S 0x0000001CU

Definition at line 188 of file netx_drv_eth_xpic_def.h.

#define REL_Adr_XPIC_RAM_ETH_CONFIG 0x00000438U

Definition at line 275 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_ETH_TX_CONFIG 0x0000043CU

Definition at line 289 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_FRAMEBUF_DATA_SIZE 0x00000468U

Definition at line 451 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_FRAMEBUF_SIZE 0x00000408U

Definition at line 105 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_FRMBUF_ADDR 0x00000404U

Definition at line 91 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_FRMBUF_ADDR_NEG 0x0000046CU

Definition at line 465 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_IRQ_STACK_PC 0x000005D0U

Definition at line 695 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_IRQ_STACK_R0 0x000005D8U

Definition at line 723 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_IRQ_STACK_REQ_HOST 0x000005DCU

Definition at line 737 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_IRQ_STACK_STAT 0x000005D4U

Definition at line 709 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_LOCAL_MAC_ADDRESS_HI 0x0000042CU

Definition at line 231 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_LOCAL_MAC_ADDRESS_LO 0x00000430U

Definition at line 245 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MACADR_HASH_TABLE0 0x0000040CU

Definition at line 119 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MACADR_HASH_TABLE1 0x00000410U

Definition at line 133 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MACADR_HASH_TABLE2 0x00000414U

Definition at line 147 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MACADR_HASH_TABLE3 0x00000418U

Definition at line 161 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_LINK_REQ_NXT 0x0000045CU

Definition at line 401 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_MODE_REQ_NXT 0x00000460U

Definition at line 415 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_PC 0x00000470U

Definition at line 479 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_READ_PHYLINK 0x00000444U

Definition at line 317 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_READ_PHYMODE 0x00000448U

Definition at line 331 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_READ_PHYSPEED 0x0000044CU

Definition at line 345 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_REQ_CYCLE 0x00000440U

Definition at line 303 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_REQ_ID 0x00000474U

Definition at line 493 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_MIIMU_SPEED_REQ_NXT 0x00000464U

Definition at line 429 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYLINK 0x00000478U

Definition at line 507 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYLINK_MSK 0x00000450U

Definition at line 359 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYMODE 0x0000047CU

Definition at line 521 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYMODE_MSK 0x00000454U

Definition at line 373 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYSPEED 0x00000480U

Definition at line 535 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_PHYSPEED_MSK 0x00000458U

Definition at line 387 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_FILL 0x00000494U

Definition at line 613 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT 0x0000049CU

Definition at line 641 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_FRM_LEN 0x00000490U

Definition at line 599 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_FRM_STAT 0x0000048CU

Definition at line 585 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_IRQ_ADR 0x0000041CU

Definition at line 175 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_IRQ_VAL 0x00000420U

Definition at line 189 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_LEN_STAT 0x00000488U

Definition at line 571 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_OFS_IP_DATA 0x00000498U

Definition at line 627 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_RX_STATE 0x00000624U

Definition at line 943 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_SHM_ADDR 0x00000400U

Definition at line 77 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_SLOT_TIME 0x00000484U

Definition at line 549 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_ABORT_MODE 0x00000434U

Definition at line 261 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FINISH_PC 0x000005E4U

Definition at line 773 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_BUF 0x000005FCU

Definition at line 857 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_DLR 0x00000600U

Definition at line 871 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_FRAME 0x0000060CU

Definition at line 913 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_FREE 0x000005F8U

Definition at line 843 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_HI 0x00000604U

Definition at line 885 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FOLLOW_LO 0x00000608U

Definition at line 899 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT 0x000005F0U

Definition at line 815 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_IRQ_ADR 0x00000424U

Definition at line 203 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_IRQ_VAL 0x00000428U

Definition at line 217 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_LENGTH 0x000005E8U

Definition at line 787 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_LENGTH_WRITTEN 0x000005ECU

Definition at line 801 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_RETRY 0x000005F4U

Definition at line 829 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_STATE 0x00000628U

Definition at line 983 of file netx_drv_eth_xpic_ram.h.

#define REL_Adr_XPIC_RAM_TX_STATE_PC 0x000005E0U

Definition at line 759 of file netx_drv_eth_xpic_ram.h.

#define SRT_ETH_FRAMEBUF_DATA_START_VAL 0

Definition at line 213 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_ID_VAL 0

Definition at line 119 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_BUFFER_NUMBER 0

Definition at line 81 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_CON_EN 8

Definition at line 83 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_ERROR_CODE 12

Definition at line 87 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_MULTIREQ_CNT 9

Definition at line 85 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_RES 16

Definition at line 91 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_INFO_VALID 15

Definition at line 89 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_SIZE_VAL 0

Definition at line 67 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_STATE_VAL 0

Definition at line 105 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_TS_RX_NS_VAL 0

Definition at line 141 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_TS_RX_S_VAL 0

Definition at line 155 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_TS_TX_NS_VAL 0

Definition at line 177 of file netx_drv_eth_xpic_def.h.

#define SRT_ETH_FRAMEBUF_TS_TX_S_VAL 0

Definition at line 191 of file netx_drv_eth_xpic_def.h.

#define SRT_XPIC_RAM_ETH_CONFIG_VAL 0

Definition at line 278 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_ETH_TX_CONFIG_VAL 0

Definition at line 292 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_FRAMEBUF_DATA_SIZE_VAL 0

Definition at line 454 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_FRAMEBUF_SIZE_VAL 0

Definition at line 108 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_FRMBUF_ADDR_ADR 0

Definition at line 94 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_FRMBUF_ADDR_NEG_ADR 0

Definition at line 468 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_IRQ_STACK_PC_VAL 0

Definition at line 698 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_IRQ_STACK_R0_VAL 0

Definition at line 726 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_IRQ_STACK_REQ_HOST_VAL 0

Definition at line 740 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_IRQ_STACK_STAT_VAL 0

Definition at line 712 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_HI_VAL 0

Definition at line 234 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_RES1 16

Definition at line 250 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_LOCAL_MAC_ADDRESS_LO_VAL 0

Definition at line 248 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MACADR_HASH_TABLE0_ADR 0

Definition at line 122 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MACADR_HASH_TABLE1_ADR 0

Definition at line 136 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MACADR_HASH_TABLE2_RES 0

Definition at line 150 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MACADR_HASH_TABLE3_RES 0

Definition at line 164 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_LINK_REQ_NXT_VAL 0

Definition at line 404 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_MODE_REQ_NXT_VAL 0

Definition at line 418 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_PC_VAL 0

Definition at line 482 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_READ_PHYLINK_VAL 0

Definition at line 320 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_READ_PHYMODE_VAL 0

Definition at line 334 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_READ_PHYSPEED_VAL 0

Definition at line 348 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_REQ_CYCLE_TIME 0

Definition at line 306 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_REQ_ID_VAL 0

Definition at line 496 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_MIIMU_SPEED_REQ_NXT_VAL 0

Definition at line 432 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYLINK_MSK_VAL 0

Definition at line 362 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYLINK_VAL 0

Definition at line 510 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYMODE_MSK_VAL 0

Definition at line 376 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYMODE_VAL 0

Definition at line 524 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYSPEED_MSK_VAL 0

Definition at line 390 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_PHYSPEED_VAL 0

Definition at line 538 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_FILL_VAL 0

Definition at line 616 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_FRAMEBUF_DATA_LIMIT_VAL 0

Definition at line 644 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_FRM_LEN_VAL 0

Definition at line 602 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_FRM_STAT_VAL 0

Definition at line 588 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_IRQ_ADR_ADR 0

Definition at line 178 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_IRQ_VAL_VAL 0

Definition at line 192 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_LEN_STAT_VAL 0

Definition at line 574 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_OFS_IP_DATA_VAL 0

Definition at line 630 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_DATA_PARSED 10

Definition at line 966 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_DROPPED 0

Definition at line 946 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FINISH 1

Definition at line 948 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FORWARDED 11

Definition at line 968 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_LOCAL_PORT 12

Definition at line 970 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT0 4

Definition at line 954 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT1 5

Definition at line 956 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT2 6

Definition at line 958 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_FRWD_FRAME_TO_PORT3 7

Definition at line 960 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_IP_PACKET 9

Definition at line 964 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_PRIO_HI 2

Definition at line 950 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_PRIO_RT 3

Definition at line 952 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_RES1 13

Definition at line 972 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_RX_STATE_VLAN_TAG 8

Definition at line 962 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_SHM_ADDR_ADR 0

Definition at line 80 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_SLOT_TIME_VAL 0

Definition at line 552 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_ABORT_MODE_VAL 0

Definition at line 264 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FINISH_PC_VAL 0

Definition at line 776 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_BUF_VAL 0

Definition at line 860 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_DLR_VAL 0

Definition at line 874 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_FRAME_VAL 0

Definition at line 916 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_FREE_VAL 0

Definition at line 846 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_HI_VAL 0

Definition at line 888 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FOLLOW_LO_VAL 0

Definition at line 902 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_FRAMEBUF_DATA_LIMIT_VAL 0

Definition at line 818 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_IRQ_ADR_ADR 0

Definition at line 206 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_IRQ_VAL_VAL 0

Definition at line 220 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_LENGTH_VAL 0

Definition at line 790 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_LENGTH_WRITTEN_VAL 0

Definition at line 804 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_RETRY_VAL 0

Definition at line 832 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_STATE_ACTIVE 0

Definition at line 986 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_STATE_PC_VAL 0

Definition at line 762 of file netx_drv_eth_xpic_ram.h.

#define SRT_XPIC_RAM_TX_STATE_RES1 1

Definition at line 988 of file netx_drv_eth_xpic_ram.h.

#define TrlSiz_eth_xpic_prg1 XpicCode_eth_xpic_prg1[1]

Definition at line 82 of file netx_drv_eth_xpic.c.

#define TrlSrt_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[3]

Definition at line 87 of file netx_drv_eth_xpic.c.

#define TrlStp_eth_xpic_prg1 &XpicCode_eth_xpic_prg1[1797]

Definition at line 88 of file netx_drv_eth_xpic.c.

#define XC_INTRAM_START_ADDRESS 0

Definition at line 160 of file netx_drv_eth_xpic.c.

#define XcCode_eth_xpic_prg1 XpicCode_eth_xpic_prg1

Definition at line 79 of file netx_drv_eth_xpic.c.

Enumeration Type Documentation

enum DRV_ETH_XPIC_PARAM

HAL Parameter Types Parameter types used by the functions DRV_ETH_Xpic_SetParam() and DRV_ETH_Xpic_GetParam().

Enumerator
DRV_ETH_XPIC_PARAM_IRQ_MASK	Interrupt enable mask, the value should be a combination of the MSK_XPIC_SHM_IRQ_IND_... masks
DRV_ETH_XPIC_PARAM_VLAN_PRIORITIZATION	Traffic class arrangement for VLAN priority classes parameter value = 0..8 VLAN priority >= parameter value: high priority VLAN priority < parameter value: low priority
DRV_ETH_XPIC_PARAM_DSCP_PRIORITIZATION	Traffic Class arrangement for IP frames (overwrites VLAN priority) parameter value = 0..0x40 DSCP >= parameter value: high priority DSCP < parameter value : low priority parameter value = 0x00 : all DSCP frames have high priority parameter value = 0x40 : all DSCP frames have low priority
DRV_ETH_XPIC_PROMISC_MODE	Enables promiscuous mode (all frame are indicated regardless of MAC address) parameter value 0/1: disable/enable promiscuous mode
DRV_ETH_XPIC_CONNECTION_STATE	Connection state from the PHY (read only). The bit masks MSK_XPIC_SHM_CONNECTION_STATE_... define the value of this parameter. bit 0: 0/1: PHY is in 10/100 MBps mode bit 1: 0/1: PHY is in Half/Full DUPLEX mode bit 2: 0/1: Link is down/up

Definition at line 87 of file netx_drv_eth_xpic.h.

enum DRV_ETH_XPIC_RESULT

Result Codes for HAL Functions All DRV_ETH_XPIC HAL functions return one of the following values. These values shall always be evaluated by the calling function.

Enumerator
DRV_ETH_XPIC_OK	Success
DRV_ETH_XPIC_NOT_INITIALIZED	The function EthStdMax_Xpic_Initialize() was not called
DRV_ETH_XPIC_NOT_RUNNING	The function DRV_ETH_Xpic_Start() was not called
DRV_ETH_XPIC_INVALID_ARG	One or more function parameters are invalid, e.g. NULL pointers etc.
DRV_ETH_XPIC_NO_FRAME_AVAILABLE	There are currently no more frame buffers available
DRV_ETH_XPIC_INVALID_HANDLE	The frame handle in parameter hFrame is invalid

Definition at line 72 of file netx_drv_eth_xpic.h.

enum DRV_ETH_XPIC_STATE

Enumerator
DRV_ETH_XPIC_STATE_UNDEF
DRV_ETH_XPIC_STATE_RESET
DRV_ETH_XPIC_STATE_INITIALIZED
DRV_ETH_XPIC_STATE_RUNNING

Definition at line 197 of file netx_drv_eth_xpic.c.

Function Documentation

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetConfirmIrq ( uint32_t * pulIrq )

Definition at line 592 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetCounters ( XPIC_SHM_CNT_T * ptMacCounter )

Definition at line 927 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetFrame ( ETH_FRAMEBUF_T ** pptFrame )

Definition at line 625 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetMacAddr ( uint8_t * pabMacAdr )

Definition at line 471 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetParam	(	DRV_ETH_XPIC_PARAM	eParam,
		uint32_t *	pulValue
	)

Definition at line 529 of file netx_drv_eth_xpic.c.

unsigned int DRV_ETH_Xpic_GetRecvFillLevel ( bool fHiPriority )

Definition at line 803 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_GetSendCnf	(	ETH_FRAMEBUF_T **	pptFrame,
		ETH_XPIC_CNF_ERR *	pErrorCode
	)

Definition at line 749 of file netx_drv_eth_xpic.c.

unsigned int DRV_ETH_Xpic_GetSendCnfFillLevel ( void )

Definition at line 721 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_Initialize	(	DRV_ETH_XPIC_CONFIG_T const *	ptConfig,
		void *	pvUser
	)

Definition at line 252 of file netx_drv_eth_xpic.c.

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DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_ReadPhyReg	(	unsigned int	uMiimuPreamble,
		unsigned int	uMiimuMdcFreq,
		unsigned int	uMiimuRtaField,
		unsigned int	uMiimuPhyAddr,
		unsigned int	uMiimuReqAddr,
		uint16_t *	pusData,
		void *	pvUser
	)

Definition at line 974 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_Recv	(	ETH_FRAMEBUF_T **	pptFrame,
		bool	fHiPriority
	)

Definition at line 842 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_ReleaseFrame ( ETH_FRAMEBUF_T * ptFrame )

Definition at line 890 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_Reset ( void * pvUser )

Definition at line 229 of file netx_drv_eth_xpic.c.

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DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_Send	(	ETH_FRAMEBUF_T *	ptFrame,
		bool	fConfirm,
		bool	fHiPriority
	)

Definition at line 678 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_SetMacAddr ( uint8_t const * pabMacAdr )

Definition at line 433 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_SetParam	(	DRV_ETH_XPIC_PARAM	eParam,
		uint32_t	ulValue
	)

Definition at line 490 of file netx_drv_eth_xpic.c.

DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_Start ( void * pvUser )

Definition at line 570 of file netx_drv_eth_xpic.c.

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DRV_ETH_XPIC_RESULT DRV_ETH_Xpic_WritePhyReg	(	unsigned int	uMiimuPreamble,
		unsigned int	uMiimuMdcFreq,
		unsigned int	uMiimuPhyAddr,
		unsigned int	uMiimuReqAddr,
		uint16_t	usData,
		void *	pvUser
	)

Definition at line 1026 of file netx_drv_eth_xpic.c.

Variable Documentation

const uint32_t BuildTime_eth_xpic_prg1 = { 53, 55, 6, 3, 8, 119, 1567493753 }

Definition at line 1052 of file netx_drv_eth_xpic.c.

uint8_t s_abMacAdr[6] = { 0, 1, 2, 3, 4, 5 }

static

Definition at line 207 of file netx_drv_eth_xpic.c.

uint32_t* const s_apulXpicDram[] = { (uint32_t*) Addr_NX90_xpic_app_dram }

static

Definition at line 107 of file netx_drv_eth_xpic.c.

volatile DRV_ETH_XPIC_STATE s_eState = DRV_ETH_XPIC_STATE_UNDEF

static

Definition at line 206 of file netx_drv_eth_xpic.c.

ETH_XPIC_SHM_AREA_T* s_ptXpicShm = NULL

static

Definition at line 208 of file netx_drv_eth_xpic.c.

const uint32_t XpicCode_eth_xpic_prg1

Definition at line 1054 of file netx_drv_eth_xpic.c.

Data Structures

Macros

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation