1 /**************************************************************************//**
2 * @file startup_netx90_app.S
3 * @brief CMSIS Cortex-M4 Core Device Startup File for
4 * ARMCM4 Device netx90_app
7 ******************************************************************************/
9 * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
17 * www.apache.org/licenses/LICENSE-2.0
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
34 .equ Stack_Size, __STACK_SIZE
36 .equ Stack_Size, 0x00002000
42 .size __StackLimit, . - __StackLimit
44 .size __StackTop, . - __StackTop
49 .equ Heap_Size, __HEAP_SIZE
51 .equ Heap_Size, 0x00002000
59 .size __HeapBase, . - __HeapBase
61 .size __HeapLimit, . - __HeapLimit
66 .globl __Vectors_Table
69 .long __StackTop /* Top of Stack */
70 .long Reset_Handler /* Reset Handler */
71 .long NMI_Handler /* NMI Handler */
72 .long HardFault_Handler /* Hard Fault Handler */
73 .long MemManage_Handler /* MPU Fault Handler */
74 .long BusFault_Handler /* Bus Fault Handler */
75 .long UsageFault_Handler /* Usage Fault Handler */
76 .long 0 /* Reserved */
77 .long 0 /* Reserved */
78 .long 0 /* Reserved */
79 .long 0 /* Reserved */
80 .long SVC_Handler /* SVCall Handler */
81 .long DebugMon_Handler /* Debug Monitor Handler */
82 .long 0 /* Reserved */
83 .long PendSV_Handler /* PendSV Handler */
84 .long SysTick_Handler /* SysTick Handler */
86 /* External interrupts */
87 .long SW_IRQHandler /* 0: software */
88 .long TIM0_IRQHandler /* 1: timer_app0 */
89 .long TIM1_IRQHandler /* 2: timer_app1 */
90 .long TIM2_IRQHandler /* 3: timer_app2 */
91 .long SYSTIME_IRQHandler /* 4: timer_app_systime_s */
92 .long WDG_IRQHandler /* 5: wdg_app */
93 .long DMAC_IRQHandler /* 6: dmac_app */
94 .long MCP_IRQHandler /* 7: mcp_app */
95 .long UART_IRQHandler /* 8: uart */
96 .long I2C_IRQHandler /* 9: i2c-app */
97 .long I2CXPIC_IRQHandler /* 10: i2c_xpic_app */
98 .long ECC_IRQHandler /* 11: ecc_app_1bit_error */
99 .long XPICDEBUG_IRQHandler /* 12: xpic_debug_app */
100 .long WDGXPIC_IRQHandler /* 13: wdg_xpic_app_arm */
101 .long NFIFO_ARM_APP_IRQHandler/* 14: nfifo_arm_app */
102 .long IOLINK_IRQHandler /* 15: io_link_irq_xpic_app */
103 .long SPI0_IRQHandler /* 16: spi0_app */
104 .long SPI1_IRQHandler /* 17: spi1_app */
105 .long SPI2_IRQHandler /* 18: spi2_app */
106 .long SPIXPIC_IRQHandler /* 19: spi_xpic_app */
107 .long UARTAPP_IRQHandler /* 20: uart_appp */
108 .long UARTXPIC_IRQHandler /* 21: uart_xpic_app */
109 .long ASIC_IRQHandler /* 22: bod */
110 .long CLKSUP_IRQHandler /* 23: clksup_app */
111 .long SQI_IRQHandler /* 24: sqi */
112 .long HIFPIO_IRQHandler /* 25: hif_pio_arm */
113 .long ETH_IRQHandler /* 26: eth */
114 .long HASH_IRQHandler /* 27: hash */
115 .long AES_IRQHandler /* 28: aes */
116 .long MTGY_IRQHandler /* 29: mtgy */
117 .long HIFRDY_IRQHandler /* 30: hif_rdy_to */
118 .long IDPM_IRQHandler /* 31: idpm_com_host */
119 .long HSC0_IRQHandler /* 32: hanshake channel 0 */
120 .long HSC1_IRQHandler /* 33: hanshake channel 1 */
121 .long HSC2_IRQHandler /* 34: hanshake channel 2 */
122 .long HSC3_IRQHandler /* 35: hanshake channel 3 */
123 .long HSC4_IRQHandler /* 36: hanshake channel 4 */
124 .long HSC5_IRQHandler /* 37: hanshake channel 5 */
125 .long HSC6_IRQHandler /* 38: hanshake channel 6 */
126 .long HSC7_IRQHandler /* 39: hanshake channel 7 */
127 .long HSC8TO15_IRQHandler /* 40: hanshake channel 8 to 15 */
128 .long ENDAT1_IRQHandler /* 41: endat_app0 */
129 .long ENDAT2_IRQHandler /* 42: endat_app1 */
130 .long BISS0_IRQHandler /* 43: biss_app0 */
131 .long BISS1_IRQHandler /* 44: biss_app1 */
132 .long MADC0_IRQHandler /* 45: madc_seq0 */
133 .long MADC1_IRQHandler /* 46: madc_seq1 */
134 .long MADC2_IRQHandler /* 47: madc_seq2 */
135 .long MADC3_IRQHandler /* 48: madc_seq3 */
136 .long MPWM_IRQHandler /* 49: mpwm */
137 .long MENC0_IRQHandler /* 50: menc_app_irq_enc0 */
138 .long MENC1_IRQHandler /* 51: menc_app_irq_enc1 */
139 .long MENCCAP_IRQHandler /* 52: menc_app_irq_cap_mp */
140 .long MENCERR_IRQHandler /* 53: menc_app_irq_err */
141 .long GPIO0_IRQHandler /* 54: gpio_app0 */
142 .long GPIO1_IRQHandler /* 55: gpio_app1 */
143 .long GPIO2_IRQHandler /* 56: gpio_app2 */
144 .long GPIO3_IRQHandler /* 57: gpio_app3 */
145 .long GPIO4_IRQHandler /* 58: gpio_app4 */
146 .long GPIO5_IRQHandler /* 59: gpio_app5 */
147 .long GPIO6_IRQHandler /* 60: gpio_app6 */
148 .long GPIO7_IRQHandler /* 61: gpio_app7 */
149 .long GPIOTIM0_IRQHandler /* 62: gpio_app_timer0 */
150 .long GPIOTIM1_IRQHandler /* 63: gpio_app_timer1 */
151 .long GPIOTIM2_IRQHandler /* 64: gpio_app_timer2 */
152 .long PIO0_IRQHandler /* 65: pio0_app */
153 .long PIO1_IRQHandler /* 66: pio1_app */
154 .long PIO2_IRQHandler /* 67: pio2_app */
155 .long PIO3_IRQHandler /* 68: pio3_app */
156 .long XCTRIGGER0_IRQHandler /* 69: trigger_out_edge0 */
157 .long XCTRIGGER1_IRQHandler /* 70: trigger_out_edge1 */
158 .long CAN0_IRQHandler /* 71: can_ctrl0_app */
159 .long CAN1_IRQHandler /* 72: can_ctrl1_app */
160 .long SQI0_IRQHandler /* 73: sqi0_app */
161 .long SQI1_IRQHandler /* 74: sqi1_app */
162 .long CTI0_IRQHandler /* 75: cti0_arm_app */
163 .long CTI1_IRQHandler /* 76: cti1_arm_app */
164 .long FPU_IRQHandler /* 77: fpu_arm_app */
165 .long 0 /* 78: reserved */
166 .long 0 /* 79: reserved */
167 .long 0 /* 80: reserved */
168 .long 0 /* 81: reserved */
169 .long 0 /* 82: reserved */
170 .long 0 /* 83: reserved */
171 .long 0 /* 84: reserved */
172 .long 0 /* 85: reserved */
173 .long 0 /* 86: reserved */
174 .long 0 /* 87: reserved */
175 .long 0 /* 88: reserved */
176 .long 0 /* 89: reserved */
177 .long 0 /* 90: reserved */
178 .long 0 /* 91: reserved */
179 .long 0 /* 92: reserved */
180 .long 0 /* 93: reserved */
181 .long 0 /* 94: reserved */
182 .long 0 /* 95: reserved */
184 .size __Vectors, . - __Vectors
191 .type Reset_Handler, %function
193 /* The following define is used to generate an application dummy. */
194 #ifdef __GENERATE_DUMMY
197 /* Firstly it copies data from read only memory to RAM. There are two schemes
198 * to copy. One can copy more than one sections. Another can only copy
199 * one section. The former scheme needs more instructions and read-only
200 * data to implement than the latter.
201 * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */
202 #ifdef __STARTUP_COPY_MULTIPLE
203 /* Multiple sections scheme.
205 * Between symbol address __copy_table_start__ and __copy_table_end__,
206 * there are array of triplets, each of which specify:
207 * offset 0: LMA of start of a section to copy from
208 * offset 4: VMA of start of a section to copy to
209 * offset 8: size of the section to copy. Must be multiply of 4
211 * All addresses must be aligned to 4 bytes boundary.
213 ldr r4, =__copy_table_start__
214 ldr r5, =__copy_table_end__
235 /* Single section scheme.
237 * The ranges of copy from/to are specified by following symbols
238 * __etext: LMA of start of the section to copy from. Usually end of text
239 * __data_start__: VMA of start of the section to copy to
240 * __data_end__: VMA of end of the section to copy to
242 * All addresses must be aligned to 4 bytes boundary.
245 ldr r2, =__data_start__
246 ldr r3, =__data_end__
254 #endif /*__STARTUP_COPY_MULTIPLE */
256 /* This part of work usually is done in C library startup code. Otherwise,
257 * define this macro to enable it in this startup.
259 * There are two schemes too. One can clear multiple BSS sections. Another
260 * can only clear one section. The former is more size expensive than the
263 * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former.
264 * Otherwise efine macro __STARTUP_CLEAR_BSS to choose the later.
266 #ifdef __STARTUP_CLEAR_BSS_MULTIPLE
267 /* Multiple sections scheme.
269 * Between symbol address __copy_table_start__ and __copy_table_end__,
270 * there are array of tuples specifying:
271 * offset 0: Start of a BSS section
272 * offset 4: Size of this BSS section. Must be multiply of 4
274 ldr r3, =__zero_table_start__
275 ldr r4, =__zero_table_end__
293 #elif defined (__STARTUP_CLEAR_BSS)
294 /* Single BSS section scheme.
296 * The BSS section is specified by following symbols
297 * __bss_start__: start of the BSS section.
298 * __bss_end__: end of the BSS section.
300 * Both addresses must be aligned to 4 bytes boundary.
302 ldr r1, =__bss_start__
311 #endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */
313 #ifndef __NO_SYSTEM_INIT
318 #define __START _start
322 #endif /* __GENERATE_DUMMY */
324 .size Reset_Handler, . - Reset_Handler
328 .weak Default_Handler
329 .type Default_Handler, %function
332 .size Default_Handler, . - Default_Handler
334 /* Macro to define default handlers. Default handler
335 * will be weak symbol and just dead loops. They can be
336 * overwritten by other handlers */
337 .macro def_irq_handler handler_name
338 #ifdef __GENERATE_DUMMY
341 #endif /* __GENERATE_DUMMY */
342 .set \handler_name, Default_Handler
345 def_irq_handler NMI_Handler
346 def_irq_handler HardFault_Handler
347 def_irq_handler MemManage_Handler
348 def_irq_handler BusFault_Handler
349 def_irq_handler UsageFault_Handler
350 def_irq_handler SVC_Handler
351 def_irq_handler DebugMon_Handler
352 def_irq_handler PendSV_Handler
353 def_irq_handler SysTick_Handler
357 def_irq_handler SW_IRQHandler
358 def_irq_handler TIM0_IRQHandler
359 def_irq_handler TIM1_IRQHandler
360 def_irq_handler TIM2_IRQHandler
361 def_irq_handler SYSTIME_IRQHandler
362 def_irq_handler WDG_IRQHandler
363 def_irq_handler DMAC_IRQHandler
364 def_irq_handler MCP_IRQHandler
365 def_irq_handler UART_IRQHandler
366 def_irq_handler I2C_IRQHandler
367 def_irq_handler I2CXPIC_IRQHandler
368 def_irq_handler ECC_IRQHandler
369 def_irq_handler XPICDEBUG_IRQHandler
370 def_irq_handler WDGXPIC_IRQHandler
371 def_irq_handler NFIFO_ARM_APP_IRQHandler
372 def_irq_handler IOLINK_IRQHandler
373 def_irq_handler SPI0_IRQHandler
374 def_irq_handler SPI1_IRQHandler
375 def_irq_handler SPI2_IRQHandler
376 def_irq_handler SPIXPIC_IRQHandler
377 def_irq_handler UARTAPP_IRQHandler
378 def_irq_handler UARTXPIC_IRQHandler
379 def_irq_handler ASIC_IRQHandler
380 def_irq_handler CLKSUP_IRQHandler
381 def_irq_handler SQI_IRQHandler
382 def_irq_handler HIFPIO_IRQHandler
383 def_irq_handler ETH_IRQHandler
384 def_irq_handler HASH_IRQHandler
385 def_irq_handler AES_IRQHandler
386 def_irq_handler MTGY_IRQHandler
387 def_irq_handler HIFRDY_IRQHandler
388 def_irq_handler IDPM_IRQHandler
389 def_irq_handler HSC0_IRQHandler
390 def_irq_handler HSC1_IRQHandler
391 def_irq_handler HSC2_IRQHandler
392 def_irq_handler HSC3_IRQHandler
393 def_irq_handler HSC4_IRQHandler
394 def_irq_handler HSC5_IRQHandler
395 def_irq_handler HSC6_IRQHandler
396 def_irq_handler HSC7_IRQHandler
397 def_irq_handler HSC8TO15_IRQHandler
398 def_irq_handler ENDAT1_IRQHandler
399 def_irq_handler ENDAT2_IRQHandler
400 def_irq_handler BISS0_IRQHandler
401 def_irq_handler BISS1_IRQHandler
402 def_irq_handler MADC0_IRQHandler
403 def_irq_handler MADC1_IRQHandler
404 def_irq_handler MADC2_IRQHandler
405 def_irq_handler MADC3_IRQHandler
406 def_irq_handler MPWM_IRQHandler
407 def_irq_handler MENC0_IRQHandler
408 def_irq_handler MENC1_IRQHandler
409 def_irq_handler MENCCAP_IRQHandler
410 def_irq_handler MENCERR_IRQHandler
411 def_irq_handler GPIO0_IRQHandler
412 def_irq_handler GPIO1_IRQHandler
413 def_irq_handler GPIO2_IRQHandler
414 def_irq_handler GPIO3_IRQHandler
415 def_irq_handler GPIO4_IRQHandler
416 def_irq_handler GPIO5_IRQHandler
417 def_irq_handler GPIO6_IRQHandler
418 def_irq_handler GPIO7_IRQHandler
419 def_irq_handler GPIOTIM0_IRQHandler
420 def_irq_handler GPIOTIM1_IRQHandler
421 def_irq_handler GPIOTIM2_IRQHandler
422 def_irq_handler PIO0_IRQHandler
423 def_irq_handler PIO1_IRQHandler
424 def_irq_handler PIO2_IRQHandler
425 def_irq_handler PIO3_IRQHandler
426 def_irq_handler XCTRIGGER0_IRQHandler
427 def_irq_handler XCTRIGGER1_IRQHandler
428 def_irq_handler CAN0_IRQHandler
429 def_irq_handler CAN1_IRQHandler
430 def_irq_handler SQI0_IRQHandler
431 def_irq_handler SQI1_IRQHandler
432 def_irq_handler CTI0_IRQHandler
433 def_irq_handler CTI1_IRQHandler
434 def_irq_handler FPU_IRQHandler
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