Hilscher netX microcontroller driver  V0.0.5.0
Documentation of the netX driver package
ARM/startup_netx90_mpw_app.s
Go to the documentation of this file.
1 ;/**************************************************************************//**
2 ; * @file startup_netx90_app.s
3 ; * @brief CMSIS Cortex-M ARMv7-M based Core Device Startup File for
4 ; * ARMCM4 Device netx90_app
5 ; * @version V5.00
6 ; * @date 02. March 2016
7 ; ******************************************************************************/
8 ;/*
9 ; * Copyright (c) 2009-2016 ARM Limited. All rights reserved.
10 ; *
11 ; * SPDX-License-Identifier: Apache-2.0
12 ; *
13 ; * Licensed under the Apache License, Version 2.0 (the License); you may
14 ; * not use this file except in compliance with the License.
15 ; * You may obtain a copy of the License at
16 ; *
17 ; * www.apache.org/licenses/LICENSE-2.0
18 ; *
19 ; * Unless required by applicable law or agreed to in writing, software
20 ; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 ; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 ; * See the License for the specific language governing permissions and
23 ; * limitations under the License.
24 ; */
25 ;/*
26 
27 ;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
28 ;*/
29 
30 
31 ; <h> Stack Configuration
32 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
33 ; </h>
34 
35 Stack_Size EQU 0x00000400
36 
37  AREA STACK, NOINIT, READWRITE, ALIGN=3
38 Stack_Mem SPACE Stack_Size
39 __initial_sp
40 
41 
42 ; <h> Heap Configuration
43 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 ; </h>
45 
46 Heap_Size EQU 0x00000C00
47 
48  AREA HEAP, NOINIT, READWRITE, ALIGN=3
49 __heap_base
50 Heap_Mem SPACE Heap_Size
51 __heap_limit
52 
53 
54  PRESERVE8
55  THUMB
56 
57 
58 ; Vector Table Mapped to Address 0 at Reset
59 
60  AREA RESET, DATA, READONLY
61  EXPORT __Vectors
62  EXPORT __Vectors_End
63  EXPORT __Vectors_Size
64 
65 __Vectors DCD __initial_sp ; Top of Stack
66  DCD Reset_Handler ; Reset Handler
67  DCD NMI_Handler ; NMI Handler
68  DCD HardFault_Handler ; Hard Fault Handler
69  DCD MemManage_Handler ; MPU Fault Handler
70  DCD BusFault_Handler ; Bus Fault Handler
71  DCD UsageFault_Handler ; Usage Fault Handler
72  DCD 0 ; Reserved
73  DCD 0 ; Reserved
74  DCD 0 ; Reserved
75  DCD 0 ; Reserved
76  DCD SVC_Handler ; SVCall Handler
77  DCD DebugMon_Handler ; Debug Monitor Handler
78  DCD 0 ; Reserved
79  DCD PendSV_Handler ; PendSV Handler
80  DCD SysTick_Handler ; SysTick Handler
81 
82  ; External Interrupts
83  DCD SW_IRQHandler ; 0: software
84  DCD TIM0_IRQHandler ; 1: timer_app0
85  DCD TIM1_IRQHandler ; 2: timer_app1
86  DCD TIM2_IRQHandler ; 3: timer_app2
87  DCD SYSTIME_IRQHandler ; 4: timer_app_systime_s
88  DCD WDG_IRQHandler ; 5: wdg_app
89  DCD DMAC_IRQHandler ; 6: dmac_app
90  DCD MCP_IRQHandler ; 7: mcp_app
91  DCD UART_IRQHandler ; 8: uart_app
92  DCD I2C_IRQHandler ; 9: i2c-app
93  DCD I2CXPIC_IRQHandler ; 10: i2c_xpic_app
94  DCD ECC1_IRQHandler ; 11: ecc_app_1bit_error
95  DCD ECC2_IRQHandler ; 12: ecc_app_2bit_error
96  DCD XPICDEBUG_IRQHandler ; 13: xpic_debug_app
97  DCD WDGXPIC_IRQHandler ; 14: wdg_xpic_app_arm
98  DCD NFIFO_ARM_APP_IRQHandler ; 15: nfifo_arm_app
99  DCD IOLINK_IRQHandler ; 16: io_link_irq_xpic_app
100  DCD SPI0_IRQHandler ; 17: spi0_app
101  DCD SPI1_IRQHandler ; 18: spi1_app
102  DCD SPI2_IRQHandler ; 19: spi2_app
103  DCD SPIXPIC_IRQHandler ; 20: spi_xpic_app
104  DCD UARTXPIC_IRQHandler ; 21: uart_xpic_app
105  DCD ASIC_IRQHandler ; 22: bod
106  DCD SQI_IRQHandler ; 23: sqi
107  DCD HIFPIO_IRQHandler ; 24: hif_pio_arm
108  DCD FETH_IRQHandler ; 25: eth
109  DCD ADC0_IRQHandler ; 26: adc0
110  DCD ADC1_IRQHandler ; 27: adc1
111  DCD HASH_IRQHandler ; 28: hash
112  DCD AES_IRQHandler ; 29: aes
113  DCD MTGY_IRQHandler ; 30: mtgy
114  DCD HIFRDY_IRQHandler ; 31: hif_rdy_to
115  DCD GPIO0_IRQHandler ; 32: gpio_app0
116  DCD GPIO1_IRQHandler ; 33: gpio_app1
117  DCD GPIO2_IRQHandler ; 34: gpio_app2
118  DCD GPIO3_IRQHandler ; 35: gpio_app3
119  DCD GPIO4_IRQHandler ; 36: gpio_app4
120  DCD GPIO5_IRQHandler ; 37: gpio_app5
121  DCD GPIO6_IRQHandler ; 38: gpio_app6
122  DCD GPIO7_IRQHandler ; 39: gpio_app7
123  DCD GPIOTIM0_IRQHandler ; 40: gpio_app_timer0
124  DCD GPIOTIM1_IRQHandler ; 41: gpio_app_timer1
125  DCD GPIOTIM2_IRQHandler ; 42: gpio_app_timer2
126  DCD XCTRIGGER0_IRQHandler ; 43: trigger_out_edge0
127  DCD XCTRIGGER1_IRQHandler ; 44: trigger_out_edge1
128  DCD CTI0_IRQHandler ; 45: cti_arm_app0
129  DCD CTI1_IRQHandler ; 46: cti_arm_app1
130  DCD FPU_IRQHandler ; 47: fpu_arm_app
131  DCD HSC0_IRQHandler ; 48: hs_com_host_hsc0
132  DCD HSC1_IRQHandler ; 49: hs_com_host_hsc1
133  DCD HSC2_IRQHandler ; 50: hs_com_host_hsc2
134  DCD HSC3_IRQHandler ; 51: hs_com_host_hsc3
135  DCD HSC4_IRQHandler ; 52: hs_com_host_hsc4
136  DCD HSC5_IRQHandler ; 53: hs_com_host_hsc5
137  DCD HSC6_IRQHandler ; 54: hs_com_host_hsc6
138  DCD HSC7_IRQHandler ; 55: hs_com_host_hsc7
139  DCD HSC8TO15_IRQHandler ; 56: hs_com_host_hsc8to15
140  DCD IDPM_IRQHandler ; 57: idpm_com_host
141  DCD ENDAT1_IRQHandler ; 58: endat_app0
142  DCD ENDAT2_IRQHandler ; 59: endat_app1
143  DCD BISS0_IRQHandler ; 60: biss_app0
144  DCD BISS1_IRQHandler ; 61: biss_app1
145  DCD CAN0_IRQHandler ; 62: can_ctrl0_app
146  DCD CAN1_IRQHandler ; 63: can_ctrl1_app
147  DCD FIREWALL_IRQHandler ; 64: firewall
148  DCD 0 ; 65: Reserved
149  DCD 0 ; 66: Reserved
150  DCD 0 ; 67: Reserved
151  DCD 0 ; 68: Reserved
152  DCD 0 ; 69: Reserved
153  DCD 0 ; 70: Reserved
154  DCD 0 ; 71: Reserved
155  DCD 0 ; 72: Reserved
156  DCD 0 ; 73: Reserved
157  DCD 0 ; 74: Reserved
158  DCD 0 ; 75: Reserved
159  DCD 0 ; 76: Reserved
160  DCD 0 ; 77: Reserved
161  DCD 0 ; 78: Reserved
162  DCD 0 ; 79: Reserved
163  DCD 0 ; 80: Reserved
164  DCD 0 ; 81: Reserved
165  DCD 0 ; 82: Reserved
166  DCD 0 ; 83: Reserved
167  DCD 0 ; 84: Reserved
168  DCD 0 ; 85: Reserved
169  DCD 0 ; 86: Reserved
170  DCD 0 ; 87: Reserved
171  DCD 0 ; 88: Reserved
172  DCD 0 ; 89: Reserved
173  DCD 0 ; 90: Reserved
174  DCD 0 ; 91: Reserved
175  DCD 0 ; 92: Reserved
176  DCD 0 ; 93: Reserved
177  DCD 0 ; 94: Reserved
178  DCD 0 ; 95: Reserved
179 
180 __Vectors_End
181 
182 __Vectors_Size EQU __Vectors_End - __Vectors
183 
184  AREA |.text|, CODE, READONLY
185 
186 
187 ; Reset Handler
188 
189 Reset_Handler PROC
190  EXPORT Reset_Handler [WEAK]
191  IMPORT SystemInit
192  IMPORT __main
193  LDR R0, =SystemInit
194  BLX R0
195  LDR R0, =__main
196  BX R0
197  ENDP
198 
199 
200 ; Dummy Exception Handlers (infinite loops which can be modified)
201 
202 NMI_Handler\
203  PROC
204  EXPORT NMI_Handler [WEAK]
205  B .
206  ENDP
207 HardFault_Handler\
208  PROC
209  EXPORT HardFault_Handler [WEAK]
210  B .
211  ENDP
212 MemManage_Handler\
213  PROC
214  EXPORT MemManage_Handler [WEAK]
215  B .
216  ENDP
217 BusFault_Handler\
218  PROC
219  EXPORT BusFault_Handler [WEAK]
220  B .
221  ENDP
222 UsageFault_Handler\
223  PROC
224  EXPORT UsageFault_Handler [WEAK]
225  B .
226  ENDP
227 SVC_Handler\
228  PROC
229  EXPORT SVC_Handler [WEAK]
230  B .
231  ENDP
232 DebugMon_Handler\
233  PROC
234  EXPORT DebugMon_Handler [WEAK]
235  B .
236  ENDP
237 PendSV_Handler\
238  PROC
239  EXPORT PendSV_Handler [WEAK]
240  B .
241  ENDP
242 SysTick_Handler\
243  PROC
244  EXPORT SysTick_Handler [WEAK]
245  B .
246  ENDP
247 
248 Default_Handler PROC
249 
250  EXPORT SW_IRQHandler [WEAK]
251  EXPORT TIM0_IRQHandler [WEAK]
252  EXPORT TIM1_IRQHandler [WEAK]
253  EXPORT TIM2_IRQHandler [WEAK]
254  EXPORT SYSTIME_IRQHandler [WEAK]
255  EXPORT WDG_IRQHandler [WEAK]
256  EXPORT DMAC_IRQHandler [WEAK]
257  EXPORT MCP_IRQHandler [WEAK]
258  EXPORT UART_IRQHandler [WEAK]
259  EXPORT I2C_IRQHandler [WEAK]
260  EXPORT I2CXPIC_IRQHandler [WEAK]
261  EXPORT ECC1_IRQHandler [WEAK]
262  EXPORT ECC2_IRQHandler [WEAK]
263  EXPORT XPICDEBUG_IRQHandler [WEAK]
264  EXPORT WDGXPIC_IRQHandler [WEAK]
265  EXPORT NFIFO_ARM_APP_IRQHandler [WEAK]
266  EXPORT IOLINK_IRQHandler [WEAK]
267  EXPORT SPI0_IRQHandler [WEAK]
268  EXPORT SPI1_IRQHandler [WEAK]
269  EXPORT SPI2_IRQHandler [WEAK]
270  EXPORT SPIXPIC_IRQHandler [WEAK]
271  EXPORT UARTXPIC_IRQHandler [WEAK]
272  EXPORT ASIC_IRQHandler [WEAK]
273  EXPORT SQI_IRQHandler [WEAK]
274  EXPORT HIFPIO_IRQHandler [WEAK]
275  EXPORT FETH_IRQHandler [WEAK]
276  EXPORT ADC0_IRQHandler [WEAK]
277  EXPORT ADC1_IRQHandler [WEAK]
278  EXPORT HASH_IRQHandler [WEAK]
279  EXPORT AES_IRQHandler [WEAK]
280  EXPORT MTGY_IRQHandler [WEAK]
281  EXPORT HIFRDY_IRQHandler [WEAK]
282  EXPORT GPIO0_IRQHandler [WEAK]
283  EXPORT GPIO1_IRQHandler [WEAK]
284  EXPORT GPIO2_IRQHandler [WEAK]
285  EXPORT GPIO3_IRQHandler [WEAK]
286  EXPORT GPIO4_IRQHandler [WEAK]
287  EXPORT GPIO5_IRQHandler [WEAK]
288  EXPORT GPIO6_IRQHandler [WEAK]
289  EXPORT GPIO7_IRQHandler [WEAK]
290  EXPORT GPIOTIM0_IRQHandler [WEAK]
291  EXPORT GPIOTIM1_IRQHandler [WEAK]
292  EXPORT GPIOTIM2_IRQHandler [WEAK]
293  EXPORT XCTRIGGER0_IRQHandler [WEAK]
294  EXPORT XCTRIGGER1_IRQHandler [WEAK]
295  EXPORT CTI0_IRQHandler [WEAK]
296  EXPORT CTI1_IRQHandler [WEAK]
297  EXPORT FPU_IRQHandler [WEAK]
298  EXPORT HSC0_IRQHandler [WEAK]
299  EXPORT HSC1_IRQHandler [WEAK]
300  EXPORT HSC2_IRQHandler [WEAK]
301  EXPORT HSC3_IRQHandler [WEAK]
302  EXPORT HSC4_IRQHandler [WEAK]
303  EXPORT HSC5_IRQHandler [WEAK]
304  EXPORT HSC6_IRQHandler [WEAK]
305  EXPORT HSC7_IRQHandler [WEAK]
306  EXPORT HSC8TO15_IRQHandler [WEAK]
307  EXPORT IDPM_IRQHandler [WEAK]
308  EXPORT ENDAT1_IRQHandler [WEAK]
309  EXPORT ENDAT2_IRQHandler [WEAK]
310  EXPORT BISS0_IRQHandler [WEAK]
311  EXPORT BISS1_IRQHandler [WEAK]
312  EXPORT CAN0_IRQHandler [WEAK]
313  EXPORT CAN1_IRQHandler [WEAK]
314  EXPORT FIREWALL_IRQHandler [WEAK]
315 
316 SW_IRQHandler
317 TIM0_IRQHandler
318 TIM1_IRQHandler
319 TIM2_IRQHandler
320 SYSTIME_IRQHandler
321 WDG_IRQHandler
322 DMAC_IRQHandler
323 MCP_IRQHandler
324 UART_IRQHandler
325 I2C_IRQHandler
326 I2CXPIC_IRQHandler
327 ECC1_IRQHandler
328 ECC2_IRQHandler
329 XPICDEBUG_IRQHandler
330 WDGXPIC_IRQHandler
331 OSAC_IRQHandler
332 IOLINK_IRQHandler
333 SPI0_IRQHandler
334 SPI1_IRQHandler
335 SPI2_IRQHandler
336 SPIXPIC_IRQHandler
337 UARTXPIC_IRQHandler
338 ASIC_IRQHandler
339 SQI_IRQHandler
340 HIFPIO_IRQHandler
341 FETH_IRQHandler
342 ADC0_IRQHandler
343 ADC1_IRQHandler
344 HASH_IRQHandler
345 AES_IRQHandler
346 MTGY_IRQHandler
347 HIFRDY_IRQHandler
348 GPIO0_IRQHandler
349 GPIO1_IRQHandler
350 GPIO2_IRQHandler
351 GPIO3_IRQHandler
352 GPIO4_IRQHandler
353 GPIO5_IRQHandler
354 GPIO6_IRQHandler
355 GPIO7_IRQHandler
356 GPIOTIM0_IRQHandler
357 GPIOTIM1_IRQHandler
358 GPIOTIM2_IRQHandler
359 XCTRIGGER0_IRQHandler
360 XCTRIGGER1_IRQHandler
361 CTI0_IRQHandler
362 CTI1_IRQHandler
363 FPU_IRQHandler
364 HSC0_IRQHandler
365 HSC1_IRQHandler
366 HSC2_IRQHandler
367 HSC3_IRQHandler
368 HSC4_IRQHandler
369 HSC5_IRQHandler
370 HSC6_IRQHandler
371 HSC7_IRQHandler
372 HSC8TO15_IRQHandler
373 IDPM_IRQHandler
374 ENDAT1_IRQHandler
375 ENDAT2_IRQHandler
376 BISS0_IRQHandler
377 BISS1_IRQHandler
378 CAN0_IRQHandler
379 CAN1_IRQHandler
380 FIREWALL_IRQHandler
381 
382  B .
383  ENDP
384 
385 
386  ALIGN
387 
388 
389 ; User Initial Stack & Heap
390 
391  IF :DEF:__MICROLIB
392 
393  EXPORT __initial_sp
394  EXPORT __heap_base
395  EXPORT __heap_limit
396 
397  ELSE
398 
399  IMPORT __use_two_region_memory
400  EXPORT __user_initial_stackheap
401 
402 __user_initial_stackheap PROC
403  LDR R0, = Heap_Mem
404  LDR R1, =(Stack_Mem + Stack_Size)
405  LDR R2, = (Heap_Mem + Heap_Size)
406  LDR R3, = Stack_Mem
407  BX LR
408  ENDP
409 
410  ALIGN
411 
412  ENDIF
413 
414 
415  END