Home | Sitemap
deutsch | franais | italiano | 日本語 | 简体中文

Datasheets

  1. netX 10 Datasheet
    english, PDF
  2. netX - Overview
    english, PDF
  3. Design Service & Production
    english, PDF

NETX 10

netX 10 Network Controller

The netX 10 has a tri-core architecture with a high-performance 32-bit/100 MHz ARM CPU, a 32-bit/100 MHz RISC controller as universal communication system for all field buses or an Ethernet port and a further 32-bit/100 MHz RISC controller for fast signal processing. It functions as a compact single chip solution in automated devices such as O/Is, drives, sensors, ID systems, or as a gateway between an Ethernet port or field bus and an IO link or modbus, as well as an intelligent communications controller on a host CPU.

When started, the SPI controller loads the ARM program code into the internal SRAM and in the SQI mode, enables an "Execution in Place" directly from the serial Flash EPROM. The Protocol Execution Controller xPEC is optimized to the determining processing of the status machine protocol and generates the control signals of the respective network via its subordinate function unit. This is defined in the start phase by loading the respective microcode via the ARM.

In contrast to this, the Peripheral Interface Controller xPIC can be freely programmed by the user and
can access the entire address space of the netX 10. The command set includes all standard RISC instructions, expanded by a 32 x 32 bit multiplication, fast loop logic and saturation support, which are all carried out in one cycle. A second register base guarantees an interrupt latency time of only 50 nanoseconds on external signals.

All processor cores are connected via a central data switch with the internal RAM, the memory controller and the two peripheral buses. The general peripheral units, such as GPIO, timer, interrupt controller, UART, USB, SPI, I2C and the AD converter, encoder, PWMs, IO link interface for signal inputs and outputs are distributed on these. With xPIC, independent function units for fast signal processing parallel to ARM CPU, such as a PCL core equipped with a CoDeSys or a motion controller with a synchronized peripheral block can be installed.

A CORDIC unit is implemented for fast calculation of transcendent functions or coordinate transformation. 24 IO signals can be selected from the periphery block via the internal multiplexer.
The memory bus can be configured as a Dual Port Memory, as memory controller for SRAM and SDRAM or as simple PIOs. The SPI mode of the DPMs enables a fast serial access to the internal memory.

Using the standardized JTAG and ETM Interface (Embedded Trace Macrocell), all commercially available ARM development tools can be connected. Based on the Eclipse, there is a complete development environment with C compiler and comfortable operating of the internal debug unit with single step and break points via USB available. The netX 10 is specified for the expanded temperature range and it is guaranteed, that it will be in stock for ten years.

Facts at a glance:

  • 32-bit/100 MHz ARM CPU and an additional 32-bit/100 MHz RISC periphery controller for parallel signal processing as a PLC Core, Motion or IO link controller
  • All fieldbuses or Ethernet feature integrated PHY and 1588
  • Single-chip solution only requires a serial flash EPROM
  • DPM or SPI Host Interface
  • Debug unit equipped with a USB connection
  • Eclipse development environment
  • 10-year supply gaurantee
Product NETX 10
Description netX 10 Network Controller
Computer Core
Processor ARM 966E-S, 100 MIPS, ARMv5TE command set with DSP extension
Internal memory
RAM 296 kBytes partioned in 4x64 kB / 1x32 kB /1x8 kB memory blockw for parallel access to the processor core
ROM 64 KByte with Bootloader
Peripherie Interface Controller
Processor xPIC, 100MIPS, RISC, command statement with 32 x 32 bit multiplication, saturation support, fastloop logic
Tightly coupled memory 8 kbyte data, 8 kbyte commands
Interrupt reaction time 50 ns on external events by switching to second register bank
Ethernet interface
Ports 1 x 10BASE-T / 100BASE-TX, half / full duplex / IEEE 1588 time stamp
PHY Integrated, Auto-Negotiation, Auto-Crossover
Real-Time-Ethernet Ethernet/IP
Modbus IDA
Fieldbus-Interface
Systems AS-Interface / CANopen / CC-Link / CompoNet / DeviceNet / MVB / PROFIBUS
Further, network interfaces are also possible, including proprietary customer development solutions
Peripherals
IEEE 1588 System Time 32-bit second counter, 32-bit nanosecond counter
USB Revision 1.1, 12 MBaud Full-Speed, Host- or Device-Mode
UART 2x 16550 compatible max. 3 MBaud, RTS / CTS support
IC Master und Slave, max 3.4 MHz
SPI Master-Mode, max. 50 MHz
AD-Converter 2 x 4 Channels with 1MS/s Sample&Hold and 10 Bit-resolution Single ended, Common Analog Ground, external reference voltage
PWM 020 kHz/12 Bit-resolution 080 kHz/10 Bit-resolution
Encoder 2 channels/ Filter / Capture / supports precise speed measurement / Interrupt / Synchronization
General I/Os 24 x selectable via the internal multiplexer,, 3.3 V / 6 mA
Status LEDs 1 x two colors, 3.3 V / 9 mA
Host-Interface
Dual-Port-Memory Mode 8- / 16-bit data bus, configurable from 2 to 128 kByte, emulated by internal RAM
SPI Slave mode with up to 80 MHz transmission cycle
PIO-Mode 47 x / freely programmable input and output ports - if all signals are not needed in the other modes, they can function as inputs/outputs
Debug-Interface
JTAG ARM-Processor and Boundary-Scan
ETM Embedded Trace Macrocell, ETM9 V2 Medium Size
Signale geshared mit Host-Interface
Operating Requirements / Housing / Miscellaneous
System cycles 100 MHz
Signal level 3.3 V
Power supply 1.5 V for the core
3.3 V for Input/Output
Operating temperature operating 40..+85 C
Storage temperature -65C..+150C
Power consumption PHY switched off, program code in internal SRAM 0.25 W
PHY switched on, program code in external SDRAM 1.0 W
Housing FBGA, 0.8 mm raster 197 pins
Dimensions 13 x 13 mm

Copyright 2014 - Hilscher Print this page | Imprint