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Rheinstraße 15
65795 Hattersheim
Germany

Telephone:
+49 (0)6190 9907-0
Facsimile:
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E-mail:
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netX 500 - Network Controller

further Informations
netX 500 Datasheet
The netX is a highly integrated network controller with a new system architecture optimized on communication and maximum data transfer.

  • Flexible “high end” network controller
    or highly integrated single
    chip solution for machine terminals
  • Four communication channels
    as Real-Time Ethernet or
    fieldbus interface
    individually configurable
  • 32-Bit/200MHz CPU ARM 926
    with 200 MIPs computing power
    for Windows CE and Linux
  • Dual-port-memory, AD converter
    and graphic controller on chip
Based on the 32-Bit CPU ARM 926EJ-S cycled at 200 MHz, it possesses a memory management unit, caches, DSP and Java extensions. The internal memory of 144 KByte RAM and 32 KByte ROM that contains the Bootloader is sufficient for smaller applications whereas for Windows CE and Linux it is supplemented with the 32 Bit Memory Controller memory externally with SDRAM, SRAM or FLASH. The connection to a primary Host is carried out via the Dual-portmemory interface, which is configurable for stand-alone applications also as a 16 Bit extension bus. Comprehensive peripheral functions, serial interfaces such as UART, USB, SPI, I²C as well as the integrated graphic controller permit a wide spectrum of applications. Yet, it is the central data switch and the four freely configurable communication channels with their own intelligence that is the main characteristic of the netX as a "high end” network controller.

The data switch connects via five data paths to the ARM CPU and the communication, graphic and Host controllers with the memory or the peripheral units. In this way the controllers transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles.

The controllers of the four communication channels are structured on two levels and are identical to each other. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. Two channels posses an additional integrated PHY for Ethernet.

The Medium-Access-Controller xMAC sends or receives the data according to the respective bus access process and encrypts or converts these into Byte depictions.

The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. These are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a Dual-port-memory available for status information or as local data picture.

With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations and can synchronize them independently of the reaction time of the CPU – an absolutely new feature in industrial communication technology.


block diagram of the netX 500 Network Controller

core

netX 500
Processor ARM 926EJ-S, 200 MIPS, ARMv5TE-command set with DSP- and Java-extension x
Cache 16 KByte commands / 8 KByte Data x
Tightly coupled memory 8 KByte Data x
Memory Managment Unit Windows CE- and Linux-Support x

internal memory

netX 500
RAM 144 KByte, of this 16 KByte with external voltage supply x
ROM 32 KByte with Bootloader x

Ethernet-Interface

netX 500
Ports 10BASE-T / 100BASE-TX, Half- / Full-Duplex, IEEE 1588 time stamp 2x
PHY Integrated, Auto-Negotiation, Auto-Crossover x
Real-Time-Ethernet EtherCAT with three FMMUs and four Sync-Manager x
Ethernet/IP x
Modbus IDA x
Powerlink with integrated Hub x
PROFINET RT and IRT with integrated Switch x
SERCOS-III x

Fieldbus-Interface

netX 500
channels If Ethernet is not used, the communication channels are available as Fieldbus-Interfaces.The systems can be combined as desired. 2x
systems AS-interface, Master only x
CANopen / DeviceNet x
CC-Link, Slave only x
PROFIBUS, Master and Slave x

Periphery

netX 500
Color-LCD-Controller For TFT-panels, Color-STN- and Mono-STN-panels
Resolution 320 x 200 to 640 x 480, color depth 1, 2, 4, 8, 16-Bit		 x
real time clock With external voltage supply+ x
IEEE 1588 System Time 32-Bit second counter, 32-Bit Nano second counter
32-Bit second counter, 32-Bit Nano second counter
32-Bit second counter, 32-Bit Nano second counter		 x
USB Revision 1.1, 12 MBaud Full-Speed, Host- or Device-Mode x
UART 16550 compatible, max. 3 MBaud, RTS/CTS support 3x
I2C    x
SPI Master- and Slave-Mode, max. 10 MHz, 3 Chip-Select-Signals x
AD-Converter 2 x 4 Channels with 1MS/s Sample&Hold and 10 Bit-resolution
Single ended, Common Analog Ground, external reference voltage		 x
PWM 0–20 kHz/12-Bit-resolution 0–80 kHz/10-Bit-resolution x
Encoder 2 Channels, Impuls quadruplication, digital input filter x
General I/Os 3.3 V / 6 mA 16x
Status LEDs 2 LEDs two-colors, 3.3 V / 9 mA x

Memory-Interface

netX 500
Memory bus 32-Bit-Databus / 24-Bit-Address bus x
Address region 256 MByte SDRAM / 64 MByte Flash x
Memory modules SDRAM, SRAM, FLASH x

Host-Interface

netX 500
Dual-port-memory-mode 8 / 16 Bit-Databus, 64 KByte configurable in 8 Blocks, emulated by internal RAM x
Extension-Mode 8/16-Bit-Databus, 24-Bit-Address bus, Bustiming adjustable x
PIO-Mode Freely programmable Inputs and Outputs 53x

Debug-Interface

netX 500
JTAG ARM-Processor and Boundary-Scan x
ETM Embedded Trace Macrocell, ETM9 V2 Medium Size x

Operating conditions / housings / various data

netX 500
System cycles 200 MHz ARM / 100 MHz Periphery
Signal level 3.3 V
Power supply 1.5 V for Core
3.3 V for Input/Output
Operating temperature without heat sink
with heat sink 10°/W		 –40.. +70 °C
–40°..+85 °C
Power consumption PHYs switched off
PHYs switched on		 1.0 W
1.5 W
Housing PBGA, 1 mm raster 345 Pins
Dimensions 22 x 22 mm
 
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