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Hilscher GmbH
Rheinstraße 15
65795 Hattersheim
Germany
Telephone:
+49 (0)6190 9907-0
Facsimile:
+49 (0)6190 9907-50
E-mail:
info@hilscher.com |
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netX 5 – Network Access Controller |
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| further Informations |
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netX 5 Datasheet |
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The netX is a highly integrated network controller with a new system architecture optimized on communication and maximum data transfer.
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- Flexible Network Access
Controller
- Two communication channels configurable between Real-Time Ethernet and fieldbus
- Two MII Ports with IEEE 1588 for EtherCAT with 8x Sync / FMMU Powerlink with integrated hub PROFINET IRT with 2-Port switch SERCOS III and others
- Fieldbus controller for
AS-Interface
CANopen and DeviceNet
CC-Link
PROFIBUS
- 8/16/32 Bit Dual-port-memory
or serial SPI Host interface
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With its integrated Dual-port-memory or the serial SPI interface, it operates as a companion chip to a Host CPU and makes available the whole spectrum of industrial communication from fieldbus up to the various Real-Time Ethernet systems. External PHYs must be connected to the two MII interface for Ethernet
purposes.
Both transmission channels are used for Real-Time Ethernet, whereas these can be combined as required when configuring as fieldbus controllers. Also of interest is a common controller for Ethernet/IP and DeviceNet, which, with the integrated IEEE 1588 unit, also supports CIP Sync.
The areas of application are communication interfaces in which the Host processor has sufficient computing power to process the whole transmission protocol.
The communication channels are designed to be compatible with the other controllers of the netX family.
They consist of dedicated ALUs and special logic units, which are allocated their respective protocol functions by means of microcode.
The xMAC Medium-Access-Controller transmits or receives data in accordance with the respective bus access procedures and codes or converts these into a Byte depiction.
The xPEC Protocol Execution Controller combines these into data packets and controls the telegram traffic. Large data quantities are transmitted per DMA blocks into, or out of, the integrated buffer memory whilst a Dual-port-memory is available for each channel for status information. Alternatively a Tripple-Buffer logic is implemented, which always provides the address of the next free buffer for purposes of conflict-free data exchange.
With the intelligent communication ALUs, the netX processes the most varied protocols and protocol combinations in a single chip – an absolutely new feature in industrial
communication technology.
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| block diagram of the netX 5 Network Access Controller |
Internal Memory
Ethernet-Interface
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netX 5 |
| Ports |
MII, 25 MHz PHY Clout output,
IEEE 1588 time stamp |
2x |
| Real-Time-Ethernet |
EtherCAT with eight FMMUs and eight Sync-Manager |
x |
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Ethernet/IP |
x |
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Modbus IDA |
x |
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Powerlink with integrated Hub |
x |
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PROFINET RT and IRT with integrated Switch |
x |
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SERCOS-III |
x |
| Synchronisation signal |
Trigger, Sample |
x |
Fieldbus-Interface
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netX 5 |
| channels |
In place of Ethernet, each channel can be configured as a fieldbus controller |
2x |
| systems |
AS-interface, Master only |
x |
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CANopen / DeviceNet, Master and Slave |
x |
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CC-Link, Slave only |
x |
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PROFIBUS, Master and Slave |
x |
Periphery
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netX 5 |
| IEEE 1588 System Time |
32-Bit second counter, 32-Bit Nano second counter
32-Bit second counter, 32-Bit Nano second counter
32-Bit second counter, 32-Bit Nano second counter |
x |
| SPI |
Master-Mode, max. 50 MHz
Slave-Mode, max. 33 MHz |
x |
| General I/Os |
3.3 V / 6 mA |
16x |
Host-Interface
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netX 5 |
| Dual-port-Memory |
8 / 16 / 32-Bit-Databus, configurable, emulated by internal RAM
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x |
| SPI |
Slave-Mode, max. 33 MHz |
x |
Debug-Interface
Operating conditions / housings / various data
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netX 5 |
| System cycles |
100 MHz |
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| Signal level |
3.3 V |
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| Power supply |
1.8 V for Core |
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3.3 V for Input/Output |
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| Temperature |
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–40°..+85 °C |
| Power consumption |
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tbd |
| Housing |
LBGA, 1 mm raster |
228 Pins |
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Dimensions |
17 x 17 mm |
performance of the netX 5 Network Access Controller
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